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Wikipedia

Tegra

January 15, 2023

For the genus of bush cricket, see Tegra (katydid).

Tegra is a system on a chip (SoC) series developed by Nvidia for mobile devices such as smartphones, personal digital assistants, and mobile Internet devices. The Tegra integrates an ARM architecture central processing unit (CPU), graphics processing unit (GPU), northbridge, southbridge, and memory controller onto one package. Early Tegra SoCs are designed as efficient multimedia processors. The Tegra-line evolved to emphasize performance for gaming and machine learning applications without sacrificing power efficiency, before taking a drastic shift in direction towards platforms that provide vehicular automation with the applied "Drive" brand name on reference boards and its semiconductors; and with the "Jetson" brand name for boards adequate for AI applications within e.g. robots or drones, and for various smart high level automation purposes.

NVIDIA Tegra T20 (Tegra 2) and T30 (Tegra 3) chips
A Tegra X1 inside a Shield TV

History

The Tegra APX 2500 was announced on February 12, 2008. The Tegra 6xx product line was revealed on June 2, 2008,[1] and the APX 2600 was announced in February 2009. The APX chips were designed for smartphones, while the Tegra 600 and 650 chips were intended for smartbooks and mobile Internet devices (MID).[2]

The first product to use the Tegra was Microsoft's Zune HD media player in September 2009, followed by the Samsung M1.[3] Microsoft's Kin was the first cellular phone to use the Tegra;[4] however, the phone did not have an app store, so the Tegra's power did not provide much advantage. In September 2008, Nvidia and Opera Software announced that they would produce a version of the Opera 9.5 browser optimized for the Tegra on Windows Mobile and Windows CE.[5][6] At Mobile World Congress 2009, Nvidia introduced its port of Google's Android to the Tegra.

On January 7, 2010, Nvidia officially announced and demonstrated its next generation Tegra system-on-a-chip, the Nvidia Tegra 250, at Consumer Electronics Show 2010.[7] Nvidia primarily supports Android on Tegra 2, but booting other ARM-supporting operating systems is possible on devices where the bootloader is accessible. Tegra 2 support for the Ubuntu Linux distribution was also announced on the Nvidia developer forum.[8]

Nvidia announced the first quad-core SoC at the February 2011 Mobile World Congress event in Barcelona. Though the chip was codenamed Kal-El, it is now branded as Tegra 3. Early benchmark results show impressive gains over Tegra 2,[9][10] and the chip was used in many of the tablets released in the second half of 2011.

In January 2012, Nvidia announced that Audi had selected the Tegra 3 processor for its In-Vehicle Infotainment systems and digital instruments display.[11] The processor will be integrated into Audi's entire line of vehicles worldwide, beginning in 2013. The process is ISO 26262-certified.[12]

In summer of 2012 Tesla Motors began shipping the Model S all electric, high performance sedan, which contains two NVIDIA Tegra 3D Visual Computing Modules (VCM). One VCM powers the 17-inch touchscreen infotainment system, and one drives the 12.3-inch all digital instrument cluster."[13]

In March 2015, Nvidia announced the Tegra X1, the first SoC to have a graphics performance of 1 teraflop. At the announcement event, Nvidia showed off Epic Games' Unreal Engine 4 "Elemental" demo, running on a Tegra X1.

On October 20, 2016, Nvidia announced that the Nintendo Switch hybrid video game console will be powered by Tegra hardware.[14] On March 15, 2017, TechInsights revealed the Nintendo Switch is powered by a custom Tegra X1 (model T210), with lower clockspeeds.[15]

Specifications

Tegra APX

Tegra APX 2500
Tegra APX 2600
  • Enhanced NAND flash
  • Video codecs:[16]
    • 720p H.264 Baseline Profile encode or decode
    • 720p VC-1/WMV9 Advanced Profile decode
    • D-1 MPEG-4 Simple Profile encode or decode

Tegra 6xx

Tegra 600
  • Targeted for GPS segment and automotive
  • Processor: ARM11 700 MHz MPCore
  • Memory: low-power DDR (DDR-333, 166 MHz)
  • SXGA, HDMI, USB, stereo jack
  • HD camera 720p
Tegra 650
  • Targeted for GTX of handheld and notebook
  • Processor: ARM11 800 MHz MPCore
  • Low power DDR (DDR-400, 200 MHz)
  • Less than 1 watt envelope
  • HD image processing for advanced digital still camera and HD camcorder functions
  • Display supports 1080p at 24 frame/s, HDMI v1.3, WSXGA+ LCD and CRT, and NTSC/PAL TV output
  • Direct support for Wi-Fi, disk drives, keyboard, mouse, and other peripherals
  • A complete board support package (BSP) to enable fast time to market for Windows Mobile-based designs

Tegra 2

 
nVidia Tegra 2 T20

The second generation Tegra SoC has a dual-core ARM Cortex-A9 CPU, an ultra low power (ULP) GeForce GPU,[17] a 32-bit memory controller with either LPDDR2-600 or DDR2-667 memory, a 32KB/32KB L1 cache per core and a shared 1MB L2 cache.[18] Tegra 2's Cortex A9 implementation does not include ARM's SIMD extension, NEON. There is a version of the Tegra 2 SoC supporting 3D displays; this SoC uses a higher clocked CPU and GPU.

The Tegra 2 video decoder is largely unchanged from the original Tegra and has limited support for HD formats.[19] The lack of support for high-profile H.264 is particularly troublesome when using online video streaming services.

Common features:

  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
  • 40 nm semiconductor technology
Model
number 		CPU GPU Memory Adoption
Processor Cores Frequency Micro-
architecture 		Core
configuration1		 Frequency Type Amount Bus
width 		Band-
width 		Availability
AP20H (Ventana/Unknown) Cortex-A9 2 1.0 GHz VLIW-based
VEC4 units[20]		 4:4:4:4[21] 300 MHz LPDDR2 300 MHz
DDR2 333 MHz		 ? 32 bit
single-channel		 2.4 GB/s
2.7 GB/s 		Q1 2010
T20 (Harmony/Ventana) 333 MHz
AP25 1.2 GHz 400 MHz Q1 2011
T25

1 Pixel shaders : Vertex shaders : Texture mapping units : Render output units

Devices

Tegra 3

 
The Ouya uses a Tegra 3 T33-P-A3

NVIDIA's Tegra 3 (codenamed "Kal-El")[28] is functionally a SoC with a quad-core ARM Cortex-A9 MPCore CPU, but includes a fifth "companion" core in what Nvidia refers to as a "variable SMP architecture".[29] While all cores are Cortex-A9s, the companion core is manufactured with a low-power silicon process. This core operates transparently to applications and is used to reduce power consumption when processing load is minimal. The main quad-core portion of the CPU powers off in these situations.

Tegra 3 is the first Tegra release to support ARM's SIMD extension, NEON.

The GPU in Tegra 3 is an evolution of the Tegra 2 GPU, with 4 additional pixel shader units and higher clock frequency. It can also output video up to 2560×1600 resolution and supports 1080p MPEG-4 AVC/h.264 40 Mbit/s High-Profile, VC1-AP, and simpler forms of MPEG-4 such as DivX and Xvid.[30]

The Tegra 3 was released on November 9, 2011.[31]

Common features:

  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
  • 40 nm LPG semiconductor technology by TSMC
Model
number 		CPU GPU Memory Adoption
Processor Cores Frequency
(multi- / single-core mode) 		Micro-
architecture 		Core
configuration1		 Frequency Type Amount Bus
width 		Band-
width 		Availability
T30L Cortex-A9 4+1 1.2 GHz / up to 1.3 GHz VLIW-based
VEC4 units[20]		 8:4:8:8[32] 416 MHz DDR3-1333 ? 32 bit
single-channel		 5.3 GB/s[33] Q1 2012
T30 1.4 GHz / up to 1.5 GHz 520 MHz LPDDR2-1066
DDR3-L-1500		 ? 4.3 GB/s
6.0 GB/s[34]		 Q4 2011
AP33
T33 1.6 GHz / up to 1.7 GHz[33] DDR3-1600 ? 6.4 GB/s[33] Q2 2012

1 Pixel shaders : Vertex shaders : Texture mapping units : Render output units

Devices

Model Devices
T30L Asus Transformer Pad TF300T, Microsoft Surface, Nexus 7 (2012),[35] Sony Xperia Tablet S, Acer Iconia Tab A210, Toshiba AT300 (Excite 10),[36][unreliable source?] BLU Quattro 4.5,[37] Coolpad 9070
T30 Asus Eee Pad Transformer Prime (TF201),[38] IdeaTab K2 / LePad K2,[39] Acer Iconia Tab A510, Fuhu Inc. nabi 2 Tablet,[40] Tesla Motors models 2013~2014 center information display (CID),[26][27] Tesla Model S of 2015 instrument cluster (IC),[41] Microsoft Surface RT,[42] Lenovo IdeaPad Yoga 11,[43][44]
AP33 LG Optimus 4X HD, HTC One X, XOLO Play T1000,[45] Coolpad 8735
T33 Asus Transformer Pad Infinity (TF700T), Fujitsu ARROWS X F-02E, Ouya, HTC One X+

Tegra 4

The Tegra 4 (codenamed "Wayne") was announced on January 6, 2013 and is a SoC with a quad-core CPU, but includes a fifth low-power Cortex A15 companion core which is invisible to the OS and performs background tasks to save power. This power-saving configuration is referred to as "variable SMP architecture" and operates like the similar configuration in Tegra 3.[46]

The GeForce GPU in Tegra 4 is again an evolution of its predecessors. However, numerous feature additions and efficiency improvements were implemented. The number of processing resources was dramatically increased, and clock rate increased as well. In 3D tests, the Tegra 4 GPU is typically several times faster than that of Tegra 3.[47] Additionally, the Tegra 4 video processor has full support for hardware decoding and encoding of WebM video (up to 1080p 60Mbit/s @ 60fps).[48]

Along with Tegra 4, Nvidia also introduced i500, an optional software modem based on Nvidia's acquisition of Icera, which can be reprogrammed to support new network standards. It supports category 3 (100Mbit/s) LTE but will later be updated to Category 4 (150Mbit/s).

Common features:

  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 2 MB
  • 28 nm HPL semiconductor technology
Model
number 		CPU GPU Memory Adoption
Processor Cores Frequency Microarchitecture Core
configuration1		 Frequency Type Amount Bus
width 		Band-
width 		Availability
T114[49][unreliable source?] Cortex-A15 4+1 up to 1.9 GHz VLIW-based VEC4 units[50] 72 (48:24:4)[20][50] 672 MHz[51] DDR3L or LPDDR3 ? 32 bit dual-channel up to 14.9 GB/s (1866 MT/s data rate)[52][53] Q2 2013[54]

1 Pixel shaders : Vertex shaders : Pixel pipelines (pairs 1x TMU and 1x ROP)

Devices

Model Devices
T114 Nvidia Shield Portable, Tegra Note 7, Microsoft Surface 2, HP Slate 7 Extreme,[55] HP Slate 7 Beats Special Edition,[56] HP Slate 8 Pro,[57] HP SlateBook x2,[58] HP SlateBook 14,[59] HP Slate 21,[60] ZTE N988S, nabi Big Tab, Nuvola NP-1, Project Mojo, Asus Transformer Pad TF701T, Toshiba AT10-LE-A (Excite Pro), Vizio 10" tablet, Wexler.Terra 7, Wexler.Terra 10, Acer TA272HUL AIO, Xiaomi Mi 3 (TD-LTE version),[61] Coolpad 8970L (大观 4),[62] Audi Tablet,[63] Le Pan TC1020 10.1",[64] Matrimax iPLAY 7,[65] Kobo Arc 10HD,[66] Tesla Model S of 2015 center information display (CID)[41]

Tegra 4i

The Tegra 4i (codenamed "Grey") was announced on February 19, 2013. With hardware support for the same audio and video formats,[48] but using Cortex-A9 cores instead of Cortex-A15, the Tegra 4i is a low-power variant of the Tegra 4 and is designed for phones and tablets. Unlike its Tegra 4 counterpart, the Tegra 4i also integrates the Icera i500 LTE/HSPA+ baseband processor onto the same die.

Common features:

  • 28 nm HPM semiconductor technology
  • CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
Model
number 		CPU GPU Memory Adoption
Processor Cores Frequency Microarchitecture Core
configuration1		 Frequency Type Amount Bus
width 		Band-
width 		Availability
T148?[67] Cortex-A9 "R4" 4+1 up to 2.0 GHz VLIW-based VEC4 units[50] 60 (48:12:2)[50] 660 MHz[51] LPDDR3 32 bit single-channel 6.4–7.5 GB/s (800–933 MHz)[53] Q1 2014

1 Pixel shaders : Vertex shaders : Pixel pipelines (pairs 1x TMU and 1x ROP)

Devices
Model Devices
T148? Blackphone, LG G2 mini LTE, Wiko Highway 4G,[68] Explay 4Game,[69] Wiko Wax[70][71] QMobile Noir LT-250[72]

Tegra K1

Nvidia's Tegra K1 (codenamed "Logan") features ARM Cortex-A15 cores in a 4+1 configuration similar to Tegra 4, or Nvidia's 64-bit Project Denver dual-core processor as well as a Kepler graphics processing unit with support for Direct3D 12, OpenGL ES 3.1, CUDA 6.5, OpenGL 4.4/OpenGL 4.5, and Vulkan.[73][74] Nvidia claims that it outperforms both the Xbox 360 and the PS3, whilst consuming significantly less power.[75]

Support Adaptive Scalable Texture Compression.[76]

In late April 2014, Nvidia shipped the "Jetson TK1" development board containing a Tegra K1 SoC and running Ubuntu Linux.[77][unreliable source?]

Model
number 		CPU GPU Memory Adoption
Processor Cores Frequency Micro-
architecture 		Core
configuration1		 Frequency GFLOPS
(FP32) 		Type Amount Bus
width 		Band-
width 		Availability
T124[80] Cortex-A15 R3
(32-bit) 		4+1 up to 2.3 GHz[81] GK20A
(Kepler) 		192:8:4[82] 756–951 MHz 290–365[83] DDR3L
LPDDR3[82]		 max 8 GB
with 40-bit address extension2 		64 bit 17 GB/s[82] Q2 2014
T132 Denver
(64-bit) 		2[82] up to 2.5 GHz[81] max 8 GB ? ? Q3 2014

1 Unified Shaders : Texture mapping units : Render output units

2 ARM Large Physical Page Extension (LPAE) supports 1 TiB (240 bytes). The 8 GiB limitation is part-specific.

Devices

Model Devices
T124 Jetson TK1 development board,[84] Nvidia Shield Tablet,[85] Acer Chromebook 13,[86] HP Chromebook 14 G3,[87] Xiaomi MiPad,[88] Snail Games
OBox, UTStarcom MC8718, Google Project Tango tablet,[89] Apalis TK1 System on Module,[90] Fuze Tomahawk F1,[91] JXD Singularity S192[92]
T132 HTC Nexus 9[93][94]

In December 2015, the web page of wccftech.com published an article stating that Tesla is going to use a Tegra K1 based design derived from the template of the Nvidia Visual Computing Module (VCM) for driving the infotainment systems and providing visual driving aid in the respective vehicle models of that time.[95] This news has, as of now, found no similar successor or other clear confirmation later on in any other place on such a combination of a multimedia with an auto pilot system for these vehicle models.

Tegra X1

 
The X1 is the basis for the Nintendo Switch video game console.
 
Die shot of the Tegra X1
 
Tegra X1 in Nvidia Shield TV

Released in 2015, Nvidia's Tegra X1 (codenamed "Erista") features two cpu clusters, one with four ARM Cortex-A57 cores and the other with four ARM Cortex-A53 cores, as well as a Maxwell-based graphics processing unit.[96][97] It supports Adaptive Scalable Texture Compression.[76] Only one cluster of cores can be active at once, with the cluster switch being handled by software on the BPMP-L. Devices utilizing the Tegra X1 have only been seen to utilize the cluster with the more powerful ARM Cortex-A57 cores. The other cluster with four ARM Cortex-A53 cores cannot be accessed without first powering down the Cortex-A57 cores (both clusters must be in the CC6 off state).[98] Nvidia has removed the ARM Cortex-A53 cores from later versions of technical documentation, implying that they have been removed from the die.[99][100] The Tegra X1 was found to be vulnerable to a Fault Injection (FI) voltage glitching attack, which allowed for arbitrary code execution and homebrew software on the devices it was implemented in.[101]

A revision (codenamed "Mariko") with greater power efficiency, known officially as Tegra X1+ was released in 2019,[102] fixing the Fusée Gelée exploit. It's also known as T214 and T210B01.

Model
number 		SOC Variant Process CPU GPU Memory Adoption
Processor Cores Frequency1 Micro-
architecture 		Core
configuration2		 Frequency GFLOPS
(FP32) 		GFLOPS
(FP16) 		Type Amount3 Bus
width 		Band-
width4		 Availability
T210 ODNX02-A2

TM670D-A1

TM670M-A2

TM671D-A2

TSMC 20 nm Cortex-A57 +
Cortex-A53[106]: 753 		 A57: 4
A53: 4[106]		 A57: 2.2 GHz[107]
A53: 1.3 GHz 		GM20B
(Maxwell)[106]: 14 		 256:[106] 16:16 1000 MHz 512 1024 LPDDR3/LPDDR4 8 GB[106] 64 bit[106] 25.6 GB/s Q2 2015
TM660M-A2 A57: 1.428 GHz
A53: ? GHz 		128:16:16 921 MHz 236 472 LPDDR3?/LPDDR4: 773  4 GB March 2019
T214/T210b01 ODNX10-A1

TM675M-A1

TSMC 16 nm Cortex-A57 A57: 4 A57: 2.1 GHz[108] GM21B (Maxwell)[109] 256:16:16 1267 MHz[110] 649 1298 LPDDR4/LPDDR4X 8 GB 34.1 GB/s Q2 2019

1 CPU frequency may be clocked differently than the maximum validated by Nvidia at the OEM's discretion

2 Unified Shaders : Texture mapping units : Render output units

3 Maximum validated amout of memory, implementation is board specific

4 Maximum validated memory bandwidth, implementation is board specific

Devices

Model SOC Variant Devices
T210 ODNX02-A2 Nintendo Switch (2017, HAC-001) [111][15]
TM670D-A1 Nvidia Shield Android TV (2015)
TM670M-A2 Nvidia Shield Android TV (2017)
TM660M-A2 Jetson Nano 4GB, Jetson Nano 2GB
TM671D-A2 Google Pixel C
Un­known Nvidia Jetson TX1 development board,[112] Nvidia Drive CX & PX
T214 ODNX10-A1 Nintendo Switch (2019, HAC-001(-01)), Nintendo Switch (OLED, HEG-001), Nintendo Switch Lite (HDH-001)
TM675M-A1 Nvidia Shield Android TV (2019)

Tegra X2

Nvidia's Tegra X2[113][114] (codenamed "Parker") features Nvidia's own custom general-purpose ARMv8-compatible core Denver 2 as well as code-named Pascal graphics processing core with GPGPU support.[115] The chips are made using FinFET process technology using TSMC's 16 nm FinFET+ manufacturing process.[116][117][118]

  • CPU: Nvidia Denver2 ARMv8 (64-bit) dual-core + ARMv8 ARM Cortex-A57 quad-core (64-bit)
  • RAM: up to 8GB LPDDR4[119]
  • GPU: Pascal-based, 256 CUDA cores; type: GP10B[120]
  • TSMC 16 nm, FinFET process
  • TDP: 7.5–15 W[121]
Model
number 		CPU GPU Memory Adoption
Processor Cores Frequency Micro-
architecture 		Core
configuration1		 Frequency GFLOPS
(FP32) 		GFLOPS
(FP16) 		Type Amount Bus
width 		Band-
width 		Availability
T186 Denver2 +
Cortex-A57 		2 + 4 Denver2: 1.4–2.0 GHz
A57: 1.2–2.0 GHz 		GP10B (Pascal)[122][unreliable source?] 256:16:16 (2)[123] 854–1465 MHz 437–750 874–1500 LPDDR4 8 GB 128 bit 59.7 GB/s

1 Unified Shaders : Texture mapping units : Render output units (SM count)

Devices

Model Devices
T186 Nvidia Drive PX2 (variants),
ZF ProAI 1.1[124]
Un­known Nvidia Jetson TX2[121]
Un­known Mercedes-Benz MBUX (infotainment system)[125]
Un­known 1 unit along with 1 GPU semiconductor is part of the ECU for "Tesla vision" functionality in all Tesla vehicles since October 2016[126][127]
Un­known Magic Leap One[128][129] (mixed environment glasses)
Un­known Skydio 2 (drone)[130]

Xavier

The Xavier Tegra SoC, named after the comic book character Professor X, was announced on 28 September 2016, and by March 2019, it had been released.[131] It contains 7 billion transistors and 8 custom ARMv8 cores, a Volta GPU with 512 CUDA cores, an open sourced TPU (Tensor Processing Unit) called DLA (Deep Learning Accelerator).[132][133] It is able to encode and decode 8K Ultra HD (7680×4320). Users can configure operating modes at 10 W, 15 W, and 30 W TDP as needed and the die size is 350 mm2.[134][135][136] Nvidia confirmed the fabrication process to be 12 nm FinFET at CES 2018.[137]

  • CPU: Nvidia custom Carmel ARMv8.2-A (64-bit), 8 cores 10-wide superscalar[138]
  • GPU: Volta-based, 512 CUDA cores with 1.4 TFLOPS;[139] type: GV11B[140][120]
  • TSMC 12 nm, FinFET process[137]
  • 20 TOPS DL and 160 SPECint @ 20 W;[134] 30 TOPS DL @ 30 W[136] (TOPS DL = Deep Learning Tera-Ops)
    • 20 TOPS DL via the GPU based tensor cores
    • 10 TOPS DL (INT8) via the DLA unit that shall achieve 5 TFLOPS (FP16)[139]
  • 1.6 TOPS in the PVA unit (Programmable Vision Accelerator,[141] for StereoDisparity/OpticalFlow/ImageProcessing)
  • 1.5 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
  • Video processor for 1.2 GPix/s encoding and 1.8 GPix/s decode[139] including 8k video support[135]
  • MIPI-CSI-3 with 16 lanes[142][143]
  • 1 Gbit/s Ethernet
  • 10 Gbit/s Ethernet
Model
number 		SOC Variant CPU GPU Memory Adoption
Processor Cores Frequency Micro-
architecture 		Core
configuration1		 Frequency GFLOPS
(FP32) 		GFLOPS
(FP16) 		Type Amount Bus
width 		Band-
width 		Availability
T194[144] Un­known Carmel 8 up to 2.26 GHz GV10B[145] (Volta) 512:32:16 (8, 64)[146] 854–1377 MHz 874–1410 1748–2820 LPDDR4X 16 GB 256-bit 137 GB/s March 2019
NX (15W) TE860M-A2 2, 4 or 6 up to 1.4 GHz (Hexa and Quad Core) or up to 1.9 GHz (Dual Core) GV10B (Volta) 384:24:16 (6, 48)[147] 1100 MHz 845 1690 LPDDR4X 8 GB 128-bit 51.2 GB/s March 2020
NX (10W) 2 or 4 up to 1.2 GHz (Quad Core) or up to 1.5 GHz (Dual Core) 800 MHz 614 1229 LPDDR4X 8 GB 128-bit 51.2 GB/s March 2020

1 Unified Shaders : Texture mapping units : Render output units (SM count, Tensor Cores)

Devices

Model SOC Variant Devices
T194 Un­known Nvidia Drive Xavier (Drive PX-series)[148]
(formerly named Xavier AI Car Supercomputer)
Un­known Nvidia Drive Pegasus (Drive PX-series)[148]
Un­known Nvidia Drive AGX Xavier Developer Kit[149]
Un­known Nvidia Jetson AGX Xavier Developer Kit[150]
Un­known Nvidia Jetson Xavier[150]
TE860M-A2 Nvidia Jetson Xavier NX[151]
Un­known Nvidia Clara AGX[152] "Clara AGX is based on NVIDIA Xavier and NVIDIA Turing GPUs."[153][unreliable source?]
Un­known Bosch and Nvidia designed Self Driving System[154]
Un­known ZF ProAI[155][156]

On the Linux Kernel Mailing List, a Tegra194 based development board with type ID "P2972-0000" got reported: The board consists of the P2888 compute module and the P2822 baseboard.[157]

Orin

 
Nvidia Orin semiconductor die with annotations (preliminary)

Nvidia announced the next-gen SoC codename Orin on March 27, 2018 at GPU Technology Conference 2018.[158] It contains 17 billion transistors and 12 Arm Hercules cores and is capable of 200 INT8 TOPs @ 65W.[159]

The Drive AGX Orin board system family was announced on December 18, 2019 at GTC China 2019. Nvidia has sent papers to the press documenting that the known (from Xavier series) clock and voltage scaling on the semiconductors and by pairing multiple such chips a wider range of application can be realized with the thus resulting board concepts.[160] The vehicle company NIO got announced by Nvidia for receiving a 4 Orin chip based board design for use in their cars.[161]

The so far published specifications for Orin are:

  • CPU: 12× Arm Cortex-A78AE (Hercules) ARMv8.2-A (64-bit)[162][163]
  • GPU: Ampere-based, 2048[164] CUDA cores and 64 tensor cores; "with up to 131 Sparse TOPs of INT8 Tensor compute, and up to 5.32 FP32 TFLOPs of CUDA compute."[165]
    • 5.3 CUDA TFLOPs (FP32)[166]
    • 10.6 CUDA TFLOPs (FP16)[166]
  • Samsung 8 nm process[166]
  • 275 TOPS (INT8) DL[166]
    • 170 TOPS DL (INT8) via the GPU
    • 105 TOPS DL (INT8) via the 2x NVDLA 2.0 units (DLA, Deep Learning Accelerator)
  • 85 TOPS DL (FP16)[166]
  • 5 TOPS in the PVA v2.0 unit (Programmable Vision Accelerator for Feature Tracking)
  • 1.85 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
  • Video processor for ? GPix/s encoding and ? GPix/s decode
  • 4× 10 Gbit/s Ethernet, 1× 1 Gbit/s Ethernet

Nvidia announced the latest member of the family, "Orin Nano" in September 2022 at the GPU Technology Conference 2022.[167] The Orin product line now features SoC and SoM(System-On-Module) based on the core Orin design and scaled for different uses from 60W all the way down to 5W. While less is known about the exact SoC's that are being manufactured, Nvidia has publicly shared detailed technical specifications about the entire Jetson Orin SoM product line. These module specifications illustrate how Orin scales providing insight into future devices that contain an Orin derived SoC.

Module

(Model)

SoC Variant CPU GPU Deep Learning Memory Adoption TDP in watts
Processor Cores Frequency

(GHz)

Micro-
architecture 		Core
configuration1		 Frequency

(MHz)

TFLOPS
(FP32) 		TFLOPS
(FP16) 		TOPS

(INT8)

Type Amount Bus
width 		Band-
width 		Availability
AGX Orin 64GB [168][169] Cortex-A78AE 9MB cache[165] 12 up to 2.2[165] GA10B (Ampere) 2048:16:64 (16, 2, 8)[165] up to 1300[165] 5.32[165] 10.649 up to 275[165] LPDDR5 64 GB 256-bit 204.8 GB/s[165] Sample 2021, Kit Q1 2022, Prod Dec 2022[170] 15-60[165]
AGX Orin 32GB[170] Cortex-A78AE 6MB cache[170] 8 up to 2.2[170] GA10B (Ampere) 1792:14:56 (14, 2, 7)[170] up to 930[170] 3.365[165] 6.73 up to 200[170] LPDDR5 32 GB[170] 256-bit[170] 102.4 GB/s[170] Oct 2022[170] 15-40[170]
Orin NX 16GB[171] TE980-M[172] Cortex-A78AE 6MB cache[171] 8 up to 2[171] Ampere 1024:8:32 (8, 1, 4)[171] up to 918[171] 1.88 3.76 up to 100[171] LPDDR5 16 GB[171] 128-bit[171] 102.4 GB/s[171] Dec 2022[171] 10-25[171]
Orin NX 8GB[170] TE980-M[172] Cortex-A78AE 5.5MB cache[170] 6 up to 2[170] Ampere 1024:8:32 (8, 1, 4)[170] up to 765[170] 1.57 3.13 up to 70[170] LPDDR5 8 GB[170] 128-bit[170] 102.4 GB/s[170] Jan 2023[170] 10-20[170]
Orin Nano 8GB[170] Cortex-A78AE 5.5MB cache[170] 6 up to 1.5[170] Ampere 1024:8:32 (8, 1, 4)[170] up to 625[170] 1.28 2.56 up to 40[170] LPDDR5 8 GB[170] 128-bit[170] 68 GB/s[170] Jan 2023[170] 7-15[170]
Orin Nano 4GB[170] Cortex-A78AE 5.5MB cache[170] 6 up to 1.5[170] Ampere 512:4:16 (4, 1, 2)[170] up to 625[170] 0.64 1.28 up to 20[170] LPDDR5 4 GB[170] 64-bit[170] 34 GB/s[170] Jan 2023[170] 5-10[170]

1 Shader Processors : Ray tracing cores : Tensor Cores (SM count, GPCs, TPCs)

Devices

Model Devices Comments
T234[173] Nvidia Jetson AGX Orin[174][165]
Un­known Nvidia Jetson Orin NX[171]
Un­known Nio Adam[175][176] built from 4x Nvidia Drive Orin, totals to 48 CPU cores and 8,192 CUDA cores;
for use in vehicles ET7 in March 2022 and ET5 in September 2022
T239[177] Un­known features 8 CPU cores in a single cluster[178](vs up to 3 clusters in T234 saving die space)

Atlan (Cancelled)

 
Nvidia Atlan die with structural annotations (preliminary)

Nvidia announced the next-gen SoC codename Atlan on April 12, 2021 at GPU Technology Conference 2021.[179][180] Nvidia announced the cancellation of Atlan on September 20, 2022, and their next SoC will be Thor.[181]

Functional units known so far are:

  • Grace Next CPU[182]
  • Ada Lovelace GPU[183]
  • Bluefield DPU (Data Processing Unit)
  • other Accelerators
  • Security Engine
  • Functional Safety Island
  • On-Chip-Memory
  • External Memory Interface(s)
  • High-Speed-IO Interfaces
Model
number 		CPU GPU Deep Learning Memory Adoption
Processor Cores Frequency Micro-
architecture 		Core
configuration1		 Frequency GFLOPS
(FP32) 		GFLOPS
(FP16) 		TOPS

(INT8)

Type Amount Bus
width 		Band-
width 		Availability
? Grace-Next[184] ? ? Ada Lovelace[185] ? ? ? ? >1000[186] ? ? ? ? Cancelled[187]

Thor

Nvidia announced the next-gen SoC codename Thor on September 20, 2022 at GPU Technology Conference 2022, replacing the cancelled Atlan.[181]

Devices

Model
number 		CPU GPU Deep Learning Memory Adoption
Processor Cores Frequency Micro-
architecture 		Core
configuration1		 Frequency GFLOPS
(FP32) 		GFLOPS
(FP16) 		TOPS

(FP8)

Type Amount Bus
width 		Band-
width 		Availability
? Arm Neoverse Poseidon AE[189] ? ? Ada Lovelace[190] ? ? ? ? 2000[191] ? ? ? ? 2025[192]

Models comparison

Series/
Generation 		Tegra 2 Tegra 3 Tegra 4 Tegra 4i Tegra K1 Tegra X1 Tegra X1+ Tegra X2 Xavier Orin Atlan
(Cancelled) 		Thor
Model/Device all all all T148? T124 T132 T210 T210b01 T186 T194 T234 ? ?
CPU Instruction set ARMv7-A (32 bit) ARMv8-A (64 bit) ARMv8.2-A (64 bit) ? ARMv9.x-A (64 bit)
Cores 2 A9 4+1 A9 4+1 A15 4+1 A9 4+1 A15 2 Denver 4 A53 (disabled) + 4 A57 4 A57 2 Denver2 + 4 A57 8 Nvidia Carmel 12 Arm Cortex-A78AE (Hercules) Nvidia Grace-Next Arm Neoverse Poseidon AE[193]
L1 Cache (I / D) 32 / 32 KB 128 / 64 KB 32 / 32 KB + 64 / 32 KB 128 / 64 KB + 48 / 32 KB 128 / 64 KB 64 / 64 KB ? ?
L2 Cache 1 MB 2 MB 128 KB + 2 MB 2 MB + 2 MB 8 MB 3 MB ? ?
L3 Cache NA 4 MB 6 MB ? ?
GPU Architecture Vec4 Kepler Maxwell Pascal Volta Ampere Ada Lovelace[194] Ada Lovelace[195]
CUDA Cores 4+4* 8+4* 48+24* 48+12* 192 256 512 2048 ? ?
RAM Protocol DDR2/LPDDR2 DDR3/LPDDR2 DDR3/LPDDR3 LPDDR3/LPDDR4 LPDDR4/LPDDR4X LPDDR5 ? ?
Max. size 1 GB 2 GB 4 GB 4 GB 8 GB 8 GB 32 GB 64 GB ? ?
Bandwidth 2.7 GB/s 6.4 GB/s 7.5 GB/s 14.88 GB/s 25.6 GB/s 34.1 GB/s 59.7 GB/s 136.5 GB/s 204.8 GB/s ? ?
Process 40 nm 28 nm HPL 28 nm HPM 20 nm FF 16 nm FF 12 nm FFN 8 nm Cancelled ?

* VLIW-based Vec4: Pixel shaders + Vertex shaders. Since Kepler, Unified shaders are used.

Software support

FreeBSD

FreeBSD supports a number of different Tegra models and generations, ranging from Tegra K1,[196] to Tegra 210.[197]

Linux

Nvidia distributes proprietary device drivers for Tegra through OEMs and as part of its "Linux for Tegra" (formerly "L4T") development kit. The newer and more powerful devices of the Tegra family are now supported by Nvidia's own Vibrante Linux distribution. Vibrante comes with a larger set of Linux tools plus several Nvidia provided libraries for acceleration in the area of data processing and especially image processing for driving safety and automated driving up to the level of deep learning and neuronal networks that make e.g. heavy use of the CUDA capable accelerator blocks, and via OpenCV can make use of the NEON vector extensions of the ARM cores.

As of April 2012, due to different "business needs" from that of their GeForce line of graphics cards, Nvidia and one of their Embedded Partners, Avionic Design GmbH from Germany, are also working on submitting open-source drivers for Tegra upstream to the mainline Linux kernel.[198][199] Nvidia co-founder & CEO laid out the Tegra processor roadmap using Ubuntu Unity in GPU Technology Conference 2013.[200][unreliable source?]

By end of 2018 it is evident that Nvidia employees have contributed substantial code parts to make the T186 and T194 models run for HDMI display and audio with the upcoming official Linux kernel 4.21 in about Q1 2019. The affected software modules are the open source Nouveau and the closed source Nvidia graphics drivers along with the Nvidia proprietary CUDA interface.[201][unreliable source?]

QNX

The Drive PX2 board was announced with QNX RTOS support at the April 2016 GPU Technology Conference.[202]

Similar platforms

SoCs and platforms with comparable specifications (e.g. audio/video input, output and processing capability, connectivity, programmability, entertainment/embedded/automotive capabilities & certifications, power consumption) are:

See also

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External links

  • Official website
  • Nvidia's Tegra APX website
  • Nvidia's Tegra FAQ
  • Tegra X1 Whitepaper
  • Tegra K1 Whitepaper
  • Tegra 4 CPU Whitepaper
  • Tegra 4 GPU Whitepaper
  • Tegra 3 Whitepaper
  • Tegra 2 Whitepaper

January 15, 2023
tegra, genus, bush, cricket, katydid, system, chip, series, developed, nvidia, mobile, devices, such, smartphones, personal, digital, assistants, mobile, internet, devices, integrates, architecture, central, processing, unit, graphics, processing, unit, northb. For the genus of bush cricket see Tegra katydid Tegra is a system on a chip SoC series developed by Nvidia for mobile devices such as smartphones personal digital assistants and mobile Internet devices The Tegra integrates an ARM architecture central processing unit CPU graphics processing unit GPU northbridge southbridge and memory controller onto one package Early Tegra SoCs are designed as efficient multimedia processors The Tegra line evolved to emphasize performance for gaming and machine learning applications without sacrificing power efficiency before taking a drastic shift in direction towards platforms that provide vehicular automation with the applied Drive brand name on reference boards and its semiconductors and with the Jetson brand name for boards adequate for AI applications within e g robots or drones and for various smart high level automation purposes NVIDIA Tegra T20 Tegra 2 and T30 Tegra 3 chips A Tegra X1 inside a Shield TV Contents 1 History 2 Specifications 2 1 Tegra APX 2 2 Tegra 6xx 2 3 Tegra 2 2 3 1 Devices 2 4 Tegra 3 2 4 1 Devices 2 5 Tegra 4 2 5 1 Devices 2 5 2 Tegra 4i 2 5 2 1 Devices 2 6 Tegra K1 2 6 1 Devices 2 7 Tegra X1 2 7 1 Devices 2 8 Tegra X2 2 8 1 Devices 2 9 Xavier 2 9 1 Devices 2 10 Orin 2 10 1 Devices 2 11 Atlan Cancelled 2 12 Thor 2 12 1 Devices 3 Models comparison 4 Software support 4 1 FreeBSD 4 2 Linux 4 3 QNX 5 Similar platforms 6 See also 7 References 8 External linksHistory EditThe Tegra APX 2500 was announced on February 12 2008 The Tegra 6xx product line was revealed on June 2 2008 1 and the APX 2600 was announced in February 2009 The APX chips were designed for smartphones while the Tegra 600 and 650 chips were intended for smartbooks and mobile Internet devices MID 2 The first product to use the Tegra was Microsoft s Zune HD media player in September 2009 followed by the Samsung M1 3 Microsoft s Kin was the first cellular phone to use the Tegra 4 however the phone did not have an app store so the Tegra s power did not provide much advantage In September 2008 Nvidia and Opera Software announced that they would produce a version of the Opera 9 5 browser optimized for the Tegra on Windows Mobile and Windows CE 5 6 At Mobile World Congress 2009 Nvidia introduced its port of Google s Android to the Tegra On January 7 2010 Nvidia officially announced and demonstrated its next generation Tegra system on a chip the Nvidia Tegra 250 at Consumer Electronics Show 2010 7 Nvidia primarily supports Android on Tegra 2 but booting other ARM supporting operating systems is possible on devices where the bootloader is accessible Tegra 2 support for the Ubuntu Linux distribution was also announced on the Nvidia developer forum 8 Nvidia announced the first quad core SoC at the February 2011 Mobile World Congress event in Barcelona Though the chip was codenamed Kal El it is now branded as Tegra 3 Early benchmark results show impressive gains over Tegra 2 9 10 and the chip was used in many of the tablets released in the second half of 2011 In January 2012 Nvidia announced that Audi had selected the Tegra 3 processor for its In Vehicle Infotainment systems and digital instruments display 11 The processor will be integrated into Audi s entire line of vehicles worldwide beginning in 2013 The process is ISO 26262 certified 12 In summer of 2012 Tesla Motors began shipping the Model S all electric high performance sedan which contains two NVIDIA Tegra 3D Visual Computing Modules VCM One VCM powers the 17 inch touchscreen infotainment system and one drives the 12 3 inch all digital instrument cluster 13 In March 2015 Nvidia announced the Tegra X1 the first SoC to have a graphics performance of 1 teraflop At the announcement event Nvidia showed off Epic Games Unreal Engine 4 Elemental demo running on a Tegra X1 On October 20 2016 Nvidia announced that the Nintendo Switch hybrid video game console will be powered by Tegra hardware 14 On March 15 2017 TechInsights revealed the Nintendo Switch is powered by a custom Tegra X1 model T210 with lower clockspeeds 15 Specifications EditTegra APX Edit Tegra APX 2500Processor ARM11 600 MHz MPCore originally GeForce ULV Suffix APX formerly CSX Memory NOR or NAND flash Mobile DDR Graphics Image processor FWVGA 854 480 pixels Up to 12 megapixels camera support LCD controller supports resolutions up to 1280 1024 Storage IDE for SSD Video codecs up to 720p MPEG 4 AVC H 264 and VC 1 decoding Includes GeForce ULV support for OpenGL ES 2 0 Direct3D Mobile and programmable shaders Output HDMI VGA composite video S Video stereo jack USB USB On The GoTegra APX 2600Enhanced NAND flash Video codecs 16 720p H 264 Baseline Profile encode or decode 720p VC 1 WMV9 Advanced Profile decode D 1 MPEG 4 Simple Profile encode or decodeTegra 6xx Edit Tegra 600Targeted for GPS segment and automotive Processor ARM11 700 MHz MPCore Memory low power DDR DDR 333 166 MHz SXGA HDMI USB stereo jack HD camera 720pTegra 650Targeted for GTX of handheld and notebook Processor ARM11 800 MHz MPCore Low power DDR DDR 400 200 MHz Less than 1 watt envelope HD image processing for advanced digital still camera and HD camcorder functions Display supports 1080p at 24 frame s HDMI v1 3 WSXGA LCD and CRT and NTSC PAL TV output Direct support for Wi Fi disk drives keyboard mouse and other peripherals A complete board support package BSP to enable fast time to market for Windows Mobile based designsTegra 2 Edit nVidia Tegra 2 T20 The second generation Tegra SoC has a dual core ARM Cortex A9 CPU an ultra low power ULP GeForce GPU 17 a 32 bit memory controller with either LPDDR2 600 or DDR2 667 memory a 32KB 32KB L1 cache per core and a shared 1MB L2 cache 18 Tegra 2 s Cortex A9 implementation does not include ARM s SIMD extension NEON There is a version of the Tegra 2 SoC supporting 3D displays this SoC uses a higher clocked CPU and GPU The Tegra 2 video decoder is largely unchanged from the original Tegra and has limited support for HD formats 19 The lack of support for high profile H 264 is particularly troublesome when using online video streaming services Common features CPU cache L1 32 KB instruction 32 KB data L2 1 MB 40 nm semiconductor technologyModelnumber CPU GPU Memory AdoptionProcessor Cores Frequency Micro architecture Coreconfiguration1 Frequency Type Amount Buswidth Band width AvailabilityAP20H Ventana Unknown Cortex A9 2 1 0 GHz VLIW basedVEC4 units 20 4 4 4 4 21 300 MHz LPDDR2 300 MHzDDR2 333 MHz 32 bitsingle channel 2 4 GB s2 7 GB s Q1 2010T20 Harmony Ventana 333 MHzAP25 1 2 GHz 400 MHz Q1 2011T251 Pixel shaders Vertex shaders Texture mapping units Render output units Devices Edit This article may contain indiscriminate excessive or irrelevant examples Please improve the article by adding more descriptive text and removing less pertinent examples See Wikipedia s guide to writing better articles for further suggestions January 2018 Model DevicesAP20H Motorola Atrix 4G Motorola Droid X2 Motorola Photon LG Optimus 2X LG Optimus Dual P990 Optimus 2x SU660 Samsung Galaxy R Samsung Captivate Glide T Mobile G2X P999 Acer Iconia Tab A200 and A500 LG Optimus Pad Motorola Xoom 22 Sony Tablet S Dell Streak Pro 23 Toshiba Thrive 24 tablet T Mobile G SlateT20 Avionic Design Tamonten Processor Board 25 Notion Ink Adam tablet Olivetti OliPad 100 ViewSonic G Tablet ASUS Eee Pad Transformer Samsung Galaxy Tab 10 1 Toshiba AC100 CompuLab Trim Slice nettop Velocity Micro Cruz Tablet L510 Acer Iconia Tab A100AP25 Fusion Garage Grid 10 citation needed Un known Tesla Motors models 2013 2014 instrument cluster IC 26 27 Tegra 3 Edit The Ouya uses a Tegra 3 T33 P A3 NVIDIA s Tegra 3 codenamed Kal El 28 is functionally a SoC with a quad core ARM Cortex A9 MPCore CPU but includes a fifth companion core in what Nvidia refers to as a variable SMP architecture 29 While all cores are Cortex A9s the companion core is manufactured with a low power silicon process This core operates transparently to applications and is used to reduce power consumption when processing load is minimal The main quad core portion of the CPU powers off in these situations Tegra 3 is the first Tegra release to support ARM s SIMD extension NEON The GPU in Tegra 3 is an evolution of the Tegra 2 GPU with 4 additional pixel shader units and higher clock frequency It can also output video up to 2560 1600 resolution and supports 1080p MPEG 4 AVC h 264 40 Mbit s High Profile VC1 AP and simpler forms of MPEG 4 such as DivX and Xvid 30 The Tegra 3 was released on November 9 2011 31 Common features CPU cache L1 32 KB instruction 32 KB data L2 1 MB 40 nm LPG semiconductor technology by TSMCModelnumber CPU GPU Memory AdoptionProcessor Cores Frequency multi single core mode Micro architecture Coreconfiguration1 Frequency Type Amount Buswidth Band width AvailabilityT30L Cortex A9 4 1 1 2 GHz up to 1 3 GHz VLIW basedVEC4 units 20 8 4 8 8 32 416 MHz DDR3 1333 32 bitsingle channel 5 3 GB s 33 Q1 2012T30 1 4 GHz up to 1 5 GHz 520 MHz LPDDR2 1066DDR3 L 1500 4 3 GB s6 0 GB s 34 Q4 2011AP33T33 1 6 GHz up to 1 7 GHz 33 DDR3 1600 6 4 GB s 33 Q2 20121 Pixel shaders Vertex shaders Texture mapping units Render output units Devices Edit Model DevicesT30L Asus Transformer Pad TF300T Microsoft Surface Nexus 7 2012 35 Sony Xperia Tablet S Acer Iconia Tab A210 Toshiba AT300 Excite 10 36 unreliable source BLU Quattro 4 5 37 Coolpad 9070T30 Asus Eee Pad Transformer Prime TF201 38 IdeaTab K2 LePad K2 39 Acer Iconia Tab A510 Fuhu Inc nabi 2 Tablet 40 Tesla Motors models 2013 2014 center information display CID 26 27 Tesla Model S of 2015 instrument cluster IC 41 Microsoft Surface RT 42 Lenovo IdeaPad Yoga 11 43 44 AP33 LG Optimus 4X HD HTC One X XOLO Play T1000 45 Coolpad 8735T33 Asus Transformer Pad Infinity TF700T Fujitsu ARROWS X F 02E Ouya HTC One X Tegra 4 Edit The Tegra 4 codenamed Wayne was announced on January 6 2013 and is a SoC with a quad core CPU but includes a fifth low power Cortex A15 companion core which is invisible to the OS and performs background tasks to save power This power saving configuration is referred to as variable SMP architecture and operates like the similar configuration in Tegra 3 46 The GeForce GPU in Tegra 4 is again an evolution of its predecessors However numerous feature additions and efficiency improvements were implemented The number of processing resources was dramatically increased and clock rate increased as well In 3D tests the Tegra 4 GPU is typically several times faster than that of Tegra 3 47 Additionally the Tegra 4 video processor has full support for hardware decoding and encoding of WebM video up to 1080p 60Mbit s 60fps 48 Along with Tegra 4 Nvidia also introduced i500 an optional software modem based on Nvidia s acquisition of Icera which can be reprogrammed to support new network standards It supports category 3 100Mbit s LTE but will later be updated to Category 4 150Mbit s Common features CPU cache L1 32 KB instruction 32 KB data L2 2 MB 28 nm HPL semiconductor technologyModelnumber CPU GPU Memory AdoptionProcessor Cores Frequency Microarchitecture Coreconfiguration1 Frequency Type Amount Buswidth Band width AvailabilityT114 49 unreliable source Cortex A15 4 1 up to 1 9 GHz VLIW based VEC4 units 50 72 48 24 4 20 50 672 MHz 51 DDR3L or LPDDR3 32 bit dual channel up to 14 9 GB s 1866 MT s data rate 52 53 Q2 2013 54 1 Pixel shaders Vertex shaders Pixel pipelines pairs 1x TMU and 1x ROP Devices Edit Model DevicesT114 Nvidia Shield Portable Tegra Note 7 Microsoft Surface 2 HP Slate 7 Extreme 55 HP Slate 7 Beats Special Edition 56 HP Slate 8 Pro 57 HP SlateBook x2 58 HP SlateBook 14 59 HP Slate 21 60 ZTE N988S nabi Big Tab Nuvola NP 1 Project Mojo Asus Transformer Pad TF701T Toshiba AT10 LE A Excite Pro Vizio 10 tablet Wexler Terra 7 Wexler Terra 10 Acer TA272HUL AIO Xiaomi Mi 3 TD LTE version 61 Coolpad 8970L 大观 4 62 Audi Tablet 63 Le Pan TC1020 10 1 64 Matrimax iPLAY 7 65 Kobo Arc 10HD 66 Tesla Model S of 2015 center information display CID 41 Tegra 4i Edit The Tegra 4i codenamed Grey was announced on February 19 2013 With hardware support for the same audio and video formats 48 but using Cortex A9 cores instead of Cortex A15 the Tegra 4i is a low power variant of the Tegra 4 and is designed for phones and tablets Unlike its Tegra 4 counterpart the Tegra 4i also integrates the Icera i500 LTE HSPA baseband processor onto the same die Common features 28 nm HPM semiconductor technology CPU cache L1 32 KB instruction 32 KB data L2 1 MBModelnumber CPU GPU Memory AdoptionProcessor Cores Frequency Microarchitecture Coreconfiguration1 Frequency Type Amount Buswidth Band width AvailabilityT148 67 Cortex A9 R4 4 1 up to 2 0 GHz VLIW based VEC4 units 50 60 48 12 2 50 660 MHz 51 LPDDR3 32 bit single channel 6 4 7 5 GB s 800 933 MHz 53 Q1 20141 Pixel shaders Vertex shaders Pixel pipelines pairs 1x TMU and 1x ROP Devices Edit Model DevicesT148 Blackphone LG G2 mini LTE Wiko Highway 4G 68 Explay 4Game 69 Wiko Wax 70 71 QMobile Noir LT 250 72 Tegra K1 Edit Nvidia s Tegra K1 codenamed Logan features ARM Cortex A15 cores in a 4 1 configuration similar to Tegra 4 or Nvidia s 64 bit Project Denver dual core processor as well as a Kepler graphics processing unit with support for Direct3D 12 OpenGL ES 3 1 CUDA 6 5 OpenGL 4 4 OpenGL 4 5 and Vulkan 73 74 Nvidia claims that it outperforms both the Xbox 360 and the PS3 whilst consuming significantly less power 75 Support Adaptive Scalable Texture Compression 76 In late April 2014 Nvidia shipped the Jetson TK1 development board containing a Tegra K1 SoC and running Ubuntu Linux 77 unreliable source Processor 32 bit variant quad core ARM Cortex A15 MPCore R3 low power companion core or 64 bit variant with dual core Project Denver 78 variant once codenamed Stark 79 GPU consisting of 192 ALUs using Kepler technology 28 nm HPM process Released in Q2 2014 Power consumption 8 watts 75 Modelnumber CPU GPU Memory AdoptionProcessor Cores Frequency Micro architecture Coreconfiguration1 Frequency GFLOPS FP32 Type Amount Buswidth Band width AvailabilityT124 80 Cortex A15 R3 32 bit 4 1 up to 2 3 GHz 81 GK20A Kepler 192 8 4 82 756 951 MHz 290 365 83 DDR3LLPDDR3 82 max 8 GBwith 40 bit address extension2 64 bit 17 GB s 82 Q2 2014T132 Denver 64 bit 2 82 up to 2 5 GHz 81 max 8 GB Q3 20141 Unified Shaders Texture mapping units Render output units2 ARM Large Physical Page Extension LPAE supports 1 TiB 240 bytes The 8 GiB limitation is part specific Devices Edit Model DevicesT124 Jetson TK1 development board 84 Nvidia Shield Tablet 85 Acer Chromebook 13 86 HP Chromebook 14 G3 87 Xiaomi MiPad 88 Snail GamesOBox UTStarcom MC8718 Google Project Tango tablet 89 Apalis TK1 System on Module 90 Fuze Tomahawk F1 91 JXD Singularity S192 92 T132 HTC Nexus 9 93 94 In December 2015 the web page of wccftech com published an article stating that Tesla is going to use a Tegra K1 based design derived from the template of the Nvidia Visual Computing Module VCM for driving the infotainment systems and providing visual driving aid in the respective vehicle models of that time 95 This news has as of now found no similar successor or other clear confirmation later on in any other place on such a combination of a multimedia with an auto pilot system for these vehicle models Tegra X1 Edit The X1 is the basis for the Nintendo Switch video game console Die shot of the Tegra X1 Tegra X1 in Nvidia Shield TV Released in 2015 Nvidia s Tegra X1 codenamed Erista features two cpu clusters one with four ARM Cortex A57 cores and the other with four ARM Cortex A53 cores as well as a Maxwell based graphics processing unit 96 97 It supports Adaptive Scalable Texture Compression 76 Only one cluster of cores can be active at once with the cluster switch being handled by software on the BPMP L Devices utilizing the Tegra X1 have only been seen to utilize the cluster with the more powerful ARM Cortex A57 cores The other cluster with four ARM Cortex A53 cores cannot be accessed without first powering down the Cortex A57 cores both clusters must be in the CC6 off state 98 Nvidia has removed the ARM Cortex A53 cores from later versions of technical documentation implying that they have been removed from the die 99 100 The Tegra X1 was found to be vulnerable to a Fault Injection FI voltage glitching attack which allowed for arbitrary code execution and homebrew software on the devices it was implemented in 101 A revision codenamed Mariko with greater power efficiency known officially as Tegra X1 was released in 2019 102 fixing the Fusee Gelee exploit It s also known as T214 and T210B01 CPU ARMv8 ARM Cortex A57 quad core 64 bit unused ARM Cortex A53 quad core 64 bit GPU Maxwell based 256 core GPU Jetson Nano only 128 cores MPEG 4 HEVC VP8 encoding decoding amp VP9 decoding support 103 Jetson Nano encoders are H 265 H 264 Stereo VP8 JPEG decoders are H 265 H 264 Stereo VP8 VP9 VC 1 MPEG 2 JPEG TSMC 20 nm process for the Tegra X1 TSMC 16 nm process for the Tegra X1 TDP T210 15 W 104 with average power consumption less than 10 W 103 Jetson Nano 10 W mode 0 105 mode 1 5W only 2 CPU cores 918 MHz GPU 640 MHz Modelnumber SOC Variant Process CPU GPU Memory AdoptionProcessor Cores Frequency1 Micro architecture Coreconfiguration2 Frequency GFLOPS FP32 GFLOPS FP16 Type Amount3 Buswidth Band width4 AvailabilityT210 ODNX02 A2 TM670D A1TM670M A2TM671D A2 TSMC 20 nm Cortex A57 Cortex A53 106 753 A57 4A53 4 106 A57 2 2 GHz 107 A53 1 3 GHz GM20B Maxwell 106 14 256 106 16 16 1000 MHz 512 1024 LPDDR3 LPDDR4 8 GB 106 64 bit 106 25 6 GB s Q2 2015TM660M A2 A57 1 428 GHzA53 GHz 128 16 16 921 MHz 236 472 LPDDR3 LPDDR4 773 4 GB March 2019T214 T210b01 ODNX10 A1 TM675M A1 TSMC 16 nm Cortex A57 A57 4 A57 2 1 GHz 108 GM21B Maxwell 109 256 16 16 1267 MHz 110 649 1298 LPDDR4 LPDDR4X 8 GB 34 1 GB s Q2 20191 CPU frequency may be clocked differently than the maximum validated by Nvidia at the OEM s discretion2 Unified Shaders Texture mapping units Render output units3 Maximum validated amout of memory implementation is board specific4 Maximum validated memory bandwidth implementation is board specific Devices Edit Model SOC Variant DevicesT210 ODNX02 A2 Nintendo Switch 2017 HAC 001 111 15 TM670D A1 Nvidia Shield Android TV 2015 TM670M A2 Nvidia Shield Android TV 2017 TM660M A2 Jetson Nano 4GB Jetson Nano 2GBTM671D A2 Google Pixel CUn known Nvidia Jetson TX1 development board 112 Nvidia Drive CX amp PXT214 ODNX10 A1 Nintendo Switch 2019 HAC 001 01 Nintendo Switch OLED HEG 001 Nintendo Switch Lite HDH 001 TM675M A1 Nvidia Shield Android TV 2019 Tegra X2 Edit Nvidia s Tegra X2 113 114 codenamed Parker features Nvidia s own custom general purpose ARMv8 compatible core Denver 2 as well as code named Pascal graphics processing core with GPGPU support 115 The chips are made using FinFET process technology using TSMC s 16 nm FinFET manufacturing process 116 117 118 CPU Nvidia Denver2 ARMv8 64 bit dual core ARMv8 ARM Cortex A57 quad core 64 bit RAM up to 8GB LPDDR4 119 GPU Pascal based 256 CUDA cores type GP10B 120 TSMC 16 nm FinFET process TDP 7 5 15 W 121 Modelnumber CPU GPU Memory AdoptionProcessor Cores Frequency Micro architecture Coreconfiguration1 Frequency GFLOPS FP32 GFLOPS FP16 Type Amount Buswidth Band width AvailabilityT186 Denver2 Cortex A57 2 4 Denver2 1 4 2 0 GHzA57 1 2 2 0 GHz GP10B Pascal 122 unreliable source 256 16 16 2 123 854 1465 MHz 437 750 874 1500 LPDDR4 8 GB 128 bit 59 7 GB s1 Unified Shaders Texture mapping units Render output units SM count Devices Edit Model DevicesT186 Nvidia Drive PX2 variants ZF ProAI 1 1 124 Un known Nvidia Jetson TX2 121 Un known Mercedes Benz MBUX infotainment system 125 Un known 1 unit along with 1 GPU semiconductor is part of the ECU for Tesla vision functionality in all Tesla vehicles since October 2016 126 127 Un known Magic Leap One 128 129 mixed environment glasses Un known Skydio 2 drone 130 Xavier Edit The Xavier Tegra SoC named after the comic book character Professor X was announced on 28 September 2016 and by March 2019 it had been released 131 It contains 7 billion transistors and 8 custom ARMv8 cores a Volta GPU with 512 CUDA cores an open sourced TPU Tensor Processing Unit called DLA Deep Learning Accelerator 132 133 It is able to encode and decode 8K Ultra HD 7680 4320 Users can configure operating modes at 10 W 15 W and 30 W TDP as needed and the die size is 350 mm2 134 135 136 Nvidia confirmed the fabrication process to be 12 nm FinFET at CES 2018 137 CPU Nvidia custom Carmel ARMv8 2 A 64 bit 8 cores 10 wide superscalar 138 GPU Volta based 512 CUDA cores with 1 4 TFLOPS 139 type GV11B 140 120 TSMC 12 nm FinFET process 137 20 TOPS DL and 160 SPECint 20 W 134 30 TOPS DL 30 W 136 TOPS DL Deep Learning Tera Ops 20 TOPS DL via the GPU based tensor cores 10 TOPS DL INT8 via the DLA unit that shall achieve 5 TFLOPS FP16 139 1 6 TOPS in the PVA unit Programmable Vision Accelerator 141 for StereoDisparity OpticalFlow ImageProcessing 1 5 GPix s in the ISP unit Image Signal Processor with native full range HDR and tile processing support Video processor for 1 2 GPix s encoding and 1 8 GPix s decode 139 including 8k video support 135 MIPI CSI 3 with 16 lanes 142 143 1 Gbit s Ethernet 10 Gbit s EthernetModelnumber SOC Variant CPU GPU Memory AdoptionProcessor Cores Frequency Micro architecture Coreconfiguration1 Frequency GFLOPS FP32 GFLOPS FP16 Type Amount Buswidth Band width AvailabilityT194 144 Un known Carmel 8 up to 2 26 GHz GV10B 145 Volta 512 32 16 8 64 146 854 1377 MHz 874 1410 1748 2820 LPDDR4X 16 GB 256 bit 137 GB s March 2019NX 15W TE860M A2 2 4 or 6 up to 1 4 GHz Hexa and Quad Core or up to 1 9 GHz Dual Core GV10B Volta 384 24 16 6 48 147 1100 MHz 845 1690 LPDDR4X 8 GB 128 bit 51 2 GB s March 2020NX 10W 2 or 4 up to 1 2 GHz Quad Core or up to 1 5 GHz Dual Core 800 MHz 614 1229 LPDDR4X 8 GB 128 bit 51 2 GB s March 20201 Unified Shaders Texture mapping units Render output units SM count Tensor Cores Devices Edit Model SOC Variant DevicesT194 Un known Nvidia Drive Xavier Drive PX series 148 formerly named Xavier AI Car Supercomputer Un known Nvidia Drive Pegasus Drive PX series 148 Un known Nvidia Drive AGX Xavier Developer Kit 149 Un known Nvidia Jetson AGX Xavier Developer Kit 150 Un known Nvidia Jetson Xavier 150 TE860M A2 Nvidia Jetson Xavier NX 151 Un known Nvidia Clara AGX 152 Clara AGX is based on NVIDIA Xavier and NVIDIA Turing GPUs 153 unreliable source Un known Bosch and Nvidia designed Self Driving System 154 Un known ZF ProAI 155 156 On the Linux Kernel Mailing List a Tegra194 based development board with type ID P2972 0000 got reported The board consists of the P2888 compute module and the P2822 baseboard 157 Orin Edit Nvidia Orin semiconductor die with annotations preliminary Nvidia announced the next gen SoC codename Orin on March 27 2018 at GPU Technology Conference 2018 158 It contains 17 billion transistors and 12 Arm Hercules cores and is capable of 200 INT8 TOPs 65W 159 The Drive AGX Orin board system family was announced on December 18 2019 at GTC China 2019 Nvidia has sent papers to the press documenting that the known from Xavier series clock and voltage scaling on the semiconductors and by pairing multiple such chips a wider range of application can be realized with the thus resulting board concepts 160 The vehicle company NIO got announced by Nvidia for receiving a 4 Orin chip based board design for use in their cars 161 The so far published specifications for Orin are CPU 12 Arm Cortex A78AE Hercules ARMv8 2 A 64 bit 162 163 GPU Ampere based 2048 164 CUDA cores and 64 tensor cores with up to 131 Sparse TOPs of INT8 Tensor compute and up to 5 32 FP32 TFLOPs of CUDA compute 165 5 3 CUDA TFLOPs FP32 166 10 6 CUDA TFLOPs FP16 166 Samsung 8 nm process 166 275 TOPS INT8 DL 166 170 TOPS DL INT8 via the GPU 105 TOPS DL INT8 via the 2x NVDLA 2 0 units DLA Deep Learning Accelerator 85 TOPS DL FP16 166 5 TOPS in the PVA v2 0 unit Programmable Vision Accelerator for Feature Tracking 1 85 GPix s in the ISP unit Image Signal Processor with native full range HDR and tile processing support Video processor for GPix s encoding and GPix s decode 4 10 Gbit s Ethernet 1 1 Gbit s EthernetNvidia announced the latest member of the family Orin Nano in September 2022 at the GPU Technology Conference 2022 167 The Orin product line now features SoC and SoM System On Module based on the core Orin design and scaled for different uses from 60W all the way down to 5W While less is known about the exact SoC s that are being manufactured Nvidia has publicly shared detailed technical specifications about the entire Jetson Orin SoM product line These module specifications illustrate how Orin scales providing insight into future devices that contain an Orin derived SoC Module Model SoC Variant CPU GPU Deep Learning Memory Adoption TDP in wattsProcessor Cores Frequency GHz Micro architecture Coreconfiguration1 Frequency MHz TFLOPS FP32 TFLOPS FP16 TOPS INT8 Type Amount Buswidth Band width AvailabilityAGX Orin 64GB 168 169 Cortex A78AE 9MB cache 165 12 up to 2 2 165 GA10B Ampere 2048 16 64 16 2 8 165 up to 1300 165 5 32 165 10 649 up to 275 165 LPDDR5 64 GB 256 bit 204 8 GB s 165 Sample 2021 Kit Q1 2022 Prod Dec 2022 170 15 60 165 AGX Orin 32GB 170 Cortex A78AE 6MB cache 170 8 up to 2 2 170 GA10B Ampere 1792 14 56 14 2 7 170 up to 930 170 3 365 165 6 73 up to 200 170 LPDDR5 32 GB 170 256 bit 170 102 4 GB s 170 Oct 2022 170 15 40 170 Orin NX 16GB 171 TE980 M 172 Cortex A78AE 6MB cache 171 8 up to 2 171 Ampere 1024 8 32 8 1 4 171 up to 918 171 1 88 3 76 up to 100 171 LPDDR5 16 GB 171 128 bit 171 102 4 GB s 171 Dec 2022 171 10 25 171 Orin NX 8GB 170 TE980 M 172 Cortex A78AE 5 5MB cache 170 6 up to 2 170 Ampere 1024 8 32 8 1 4 170 up to 765 170 1 57 3 13 up to 70 170 LPDDR5 8 GB 170 128 bit 170 102 4 GB s 170 Jan 2023 170 10 20 170 Orin Nano 8GB 170 Cortex A78AE 5 5MB cache 170 6 up to 1 5 170 Ampere 1024 8 32 8 1 4 170 up to 625 170 1 28 2 56 up to 40 170 LPDDR5 8 GB 170 128 bit 170 68 GB s 170 Jan 2023 170 7 15 170 Orin Nano 4GB 170 Cortex A78AE 5 5MB cache 170 6 up to 1 5 170 Ampere 512 4 16 4 1 2 170 up to 625 170 0 64 1 28 up to 20 170 LPDDR5 4 GB 170 64 bit 170 34 GB s 170 Jan 2023 170 5 10 170 1 Shader Processors Ray tracing cores Tensor Cores SM count GPCs TPCs Devices Edit Model Devices CommentsT234 173 Nvidia Jetson AGX Orin 174 165 Un known Nvidia Jetson Orin NX 171 Un known Nio Adam 175 176 built from 4x Nvidia Drive Orin totals to 48 CPU cores and 8 192 CUDA cores for use in vehicles ET7 in March 2022 and ET5 in September 2022T239 177 Un known features 8 CPU cores in a single cluster 178 vs up to 3 clusters in T234 saving die space Atlan Cancelled Edit Nvidia Atlan die with structural annotations preliminary Nvidia announced the next gen SoC codename Atlan on April 12 2021 at GPU Technology Conference 2021 179 180 Nvidia announced the cancellation of Atlan on September 20 2022 and their next SoC will be Thor 181 Functional units known so far are Grace Next CPU 182 Ada Lovelace GPU 183 Bluefield DPU Data Processing Unit other Accelerators Security Engine Functional Safety Island On Chip Memory External Memory Interface s High Speed IO InterfacesModelnumber CPU GPU Deep Learning Memory AdoptionProcessor Cores Frequency Micro architecture Coreconfiguration1 Frequency GFLOPS FP32 GFLOPS FP16 TOPS INT8 Type Amount Buswidth Band width Availability Grace Next 184 Ada Lovelace 185 gt 1000 186 Cancelled 187 Thor Edit Nvidia announced the next gen SoC codename Thor on September 20 2022 at GPU Technology Conference 2022 replacing the cancelled Atlan 181 Devices Edit Nvidia DRIVE Thor 188 Modelnumber CPU GPU Deep Learning Memory AdoptionProcessor Cores Frequency Micro architecture Coreconfiguration1 Frequency GFLOPS FP32 GFLOPS FP16 TOPS FP8 Type Amount Buswidth Band width Availability Arm Neoverse Poseidon AE 189 Ada Lovelace 190 2000 191 2025 192 Models comparison EditSeries Generation Tegra 2 Tegra 3 Tegra 4 Tegra 4i Tegra K1 Tegra X1 Tegra X1 Tegra X2 Xavier Orin Atlan Cancelled ThorModel Device all all all T148 T124 T132 T210 T210b01 T186 T194 T234 CPU Instruction set ARMv7 A 32 bit ARMv8 A 64 bit ARMv8 2 A 64 bit ARMv9 x A 64 bit Cores 2 A9 4 1 A9 4 1 A15 4 1 A9 4 1 A15 2 Denver 4 A53 disabled 4 A57 4 A57 2 Denver2 4 A57 8 Nvidia Carmel 12 Arm Cortex A78AE Hercules Nvidia Grace Next Arm Neoverse Poseidon AE 193 L1 Cache I D 32 32 KB 128 64 KB 32 32 KB 64 32 KB 128 64 KB 48 32 KB 128 64 KB 64 64 KB L2 Cache 1 MB 2 MB 128 KB 2 MB 2 MB 2 MB 8 MB 3 MB L3 Cache NA 4 MB 6 MB GPU Architecture Vec4 Kepler Maxwell Pascal Volta Ampere Ada Lovelace 194 Ada Lovelace 195 CUDA Cores 4 4 8 4 48 24 48 12 192 256 512 2048 RAM Protocol DDR2 LPDDR2 DDR3 LPDDR2 DDR3 LPDDR3 LPDDR3 LPDDR4 LPDDR4 LPDDR4X LPDDR5 Max size 1 GB 2 GB 4 GB 4 GB 8 GB 8 GB 32 GB 64 GB Bandwidth 2 7 GB s 6 4 GB s 7 5 GB s 14 88 GB s 25 6 GB s 34 1 GB s 59 7 GB s 136 5 GB s 204 8 GB s Process 40 nm 28 nm HPL 28 nm HPM 20 nm FF 16 nm FF 12 nm FFN 8 nm Cancelled VLIW based Vec4 Pixel shaders Vertex shaders Since Kepler Unified shaders are used Software support EditFreeBSD Edit FreeBSD supports a number of different Tegra models and generations ranging from Tegra K1 196 to Tegra 210 197 Linux Edit Nvidia distributes proprietary device drivers for Tegra through OEMs and as part of its Linux for Tegra formerly L4T development kit The newer and more powerful devices of the Tegra family are now supported by Nvidia s own Vibrante Linux distribution Vibrante comes with a larger set of Linux tools plus several Nvidia provided libraries for acceleration in the area of data processing and especially image processing for driving safety and automated driving up to the level of deep learning and neuronal networks that make e g heavy use of the CUDA capable accelerator blocks and via OpenCV can make use of the NEON vector extensions of the ARM cores As of April 2012 update due to different business needs from that of their GeForce line of graphics cards Nvidia and one of their Embedded Partners Avionic Design GmbH from Germany are also working on submitting open source drivers for Tegra upstream to the mainline Linux kernel 198 199 Nvidia co founder amp CEO laid out the Tegra processor roadmap using Ubuntu Unity in GPU Technology Conference 2013 200 unreliable source By end of 2018 it is evident that Nvidia employees have contributed substantial code parts to make the T186 and T194 models run for HDMI display and audio with the upcoming official Linux kernel 4 21 in about Q1 2019 The affected software modules are the open source Nouveau and the closed source Nvidia graphics drivers along with the Nvidia proprietary CUDA interface 201 unreliable source QNX Edit The Drive PX2 board was announced with QNX RTOS support at the April 2016 GPU Technology Conference 202 Similar platforms EditSoCs and platforms with comparable specifications e g audio video input output and processing capability connectivity programmability entertainment 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