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Wikipedia

Zen (first generation)

November 19, 2023

This article is about the first generation of the Zen microarchitecture. For the CPU architecture family, see Zen (microarchitecture).

Zen is the codename for the first iteration in a family of computer processor microarchitectures of the same name from AMD. It was first used with their Ryzen series of CPUs in February 2017.[3] The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs, codenamed "Summit Ridge", reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017[10] and Zen-based APUs arrived in November 2017.[11]

AMD Zen
The logo for the Zen microarchitecture is a closed ensō
General information
LaunchedMarch 2, 2017; 6 years ago (March 2, 2017)[1]
Designed byAMD
Common manufacturer(s)
CPUID codeFamily 17h
Cache
L1 cache64 KB instruction, 32 KB data per core
L2 cache512 KB per core
L3 cache8 MB per quad-core CCX (APU: 4 MB)
Architecture and classification
Instruction setAMD64 (x86-64)
Physical specifications
Transistors
Cores
    • 2–4 (essential)
    • 4–8 (mainstream)
    • 8–16 (enthusiast)[3][4][5][6]
    • Up to 32 (server)[3][7]
Socket(s)
Products, models, variants
Product code name(s)
  • Summit Ridge (Desktop)
  • Whitehaven (HEDT)
  • Raven Ridge (APU/Embedded)
  • Naples (Server CPU)
  • Snowy Owl (Server APU)[9]
Brand name(s)
History
Predecessor(s)Excavator (4th gen)
Successor(s)Zen+
Support status
Supported

Zen is a clean sheet design that differs from AMD's previous long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop and mobile Ryzen chips use the AM4 socket, bringing DDR4 support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 RAM and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket;[12][13] and Epyc server processors offer 128 PCI 3.0 lanes and octa-channel DDR4 using the SP3 socket.

Zen is based on a SoC design.[14] The memory controller and the PCIe, SATA, and USB controllers are incorporated into the same chip(s) as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area.[15] This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.

By 2020, 260 million Zen cores have already been shipped by AMD.[16]

Design edit

 
A highly simplified illustration of the Zen microarchitecture: a core has a total of 512 KB of L2 cache.
 
Ryzen 3 1200 Die Shot
 
Photomontage of a delidded Zen CPU with an etched die.
 
A delidded AMD EPYC processor used in servers; The four dies are similar to the ones used in mainstream processors. All EPYC processors contain four dies to provide structural support to the IHS (Integrated Heat Spreader).[17][18][19]
 
A delidded AMD Athlon 3000G APU, based on the Zen architecture. The die is physically smaller than those on mainstream Zen processors.
 
Die shot of an AMD Athlon 3000G

According to AMD, the main focus of Zen is on increasing per-core performance.[20][21][22] New or improved features include:[23]

  • The L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth.
  • SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture. This is a feature previously offered in some IBM, Intel and Oracle processors.[24]
  • A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric.[25] Processors with non-multiple-of-four core counts have some cores disabled.
  • Four ALUs, two AGUs/load–store units, and two floating-point units per core.[26]
  • Newly introduced "large" micro-operation cache.[27]
  • Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle).[28][29]
  • Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×.
  • Clock gating.
  • Larger retire, load, and store queues.
  • Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture,[30] something that has been compared to a neural network by AMD engineer Mike Clark.[31]
  • The branch predictor is decoupled from the fetch stage.
  • A dedicated stack engine for modifying the stack pointer, similar to that of Intel Haswell and Broadwell processors.[32]
  • Move elimination, a method that reduces physical data movement to reduce power consumption.
  • Binary compatibility with Intel's Skylake (excluding VT-x and private MSRs):
  • CLZERO instruction for clearing a cache line.[33] Useful for handling ECC-related Machine-check exceptions.
  • PTE (page table entry) coalescing, which combines 4 kB page tables into 32 kB page size.
  • "Pure Power" (more accurate power monitoring sensors).[34]
    • Support for intel-style running average power limit (RAPL) measurement.[35]
  • Smart Prefetch.
  • Precision Boost.
  • eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.[36]

This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do. It is a multi-year project with a really large team. It's like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation.

— Suzanne Plummer, Zen team leader, on September 19th, 2015.[37]

The Zen architecture is built on a 14 nanometer FinFET process subcontracted to GlobalFoundries,[38] which in turn licenses its 14 nm process from Samsung Electronics.[39] This gives greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.[40] The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP (thermal design power).[40] While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.[41]

Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments.[42][43] Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units.[44] There are also improvements in the branch predictor. The L1 cache size is 64 KB for instructions per core and 32 KB for data per core. The L2 cache size 512 KB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs.

History and development edit

AMD began planning the Zen microarchitecture shortly after re-hiring Jim Keller in August 2012.[45] AMD formally revealed Zen in 2015.

The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer.[46][47] The Chief Architect of Zen was AMD Senior Fellow Michael Clark.[48][49][50]

Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,[8] with the release of the first Zen-based processors expected for October 2016.[51]

In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".[2][52]

In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming Polaris GPU architecture.[53] This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process.[54] AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.

In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.[55]

Advantages over predecessors edit

Manufacturing process edit

Processors based on Zen use 14 nm FinFET silicon.[56] These processors are reportedly produced at GlobalFoundries.[57] Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures.[58][59] The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET;[60] though Intel planned to begin the release of 10 nm parts later in 2017.[61] Intel was unable to reach this goal, and in 2021, only mobile chips have been produced with the 10nm process. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller.[62] Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.[63]

For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125 W, or ~45 W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.[64]

Performance edit

One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in instructions per cycle (IPC) over its predecessor.[65] Excavator, in comparison, offered 4–15% improvement over previous architectures.[66][67] AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator.[68] The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources.

The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage.[69] This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.

AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked Intel Broadwell-E processor in Blender rendering[3][9] and HandBrake benchmarks.[69]

Zen supports AVX2 but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one.[70][71] This difference was corrected in Zen 2.

Memory edit

Zen supports DDR4 memory (up to eight channels)[72] and ECC.[73]

Pre-release reports stated APUs using the Zen architecture would also support High Bandwidth Memory (HBM).[74] However, the first demonstrated APU did not use HBM.[75] Previous APUs from AMD relied on shared memory for both the GPU and the CPU.

Power consumption and heat output edit

Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.

Zen also uses clock gating,[43] reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.[69]

Enhanced security and virtualization support edit

Zen added support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption occurs on a hardware AES engine and keys are managed by the onboard "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any DDR4 memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.[76][77]

SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature.

[78]

The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.[79]

Connectivity edit

Incorporating much of the southbridge into the SoC, the Zen CPU includes SATA, USB, and PCI Express NVMe links.[80][81] This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for AMD's Crossfire and Nvidia's SLI.[82]

AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen-based Naples server CPU would be particularly suited for building deep learning systems.[83][84] The 128[85] PCIe lanes per Naples CPU allows for eight Instinct cards to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40[citation needed] PCIe lanes.

Features edit

CPUs edit

APUs edit

APU features table

Products edit

The Zen architecture is used in the current-generation desktop Ryzen CPUs. It is also in Epyc server processors (successor of Opteron processors), and APUs.[74][unreliable source][86][87]

The first desktop processors without graphics processing units (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the AMD Accelerated Processing Unit type (codenamed "Raven Ridge") following in late 2017.[88] AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8-core/16-thread engineering sample CPU at 3.0 GHz.[9]

In December 2016, AMD officially announced the desktop CPU line under the Ryzen brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.[89]

On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance-per-watt benefits over the previous K15h (Piledriver) architecture.[90][91] The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell octacore CPUs.[92][93]

In March 2017, AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture. The CPU (codenamed "Naples") was configured as a dual-socket server platform with each CPU having 32 cores/64 threads.[3][9]

Desktop processors edit

Main article: Ryzen

Common features of Ryzen 1000 desktop CPUs:

  • Socket: AM4.
  • All the CPUs support DDR4-2666 in dual-channel mode.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • Node/fabrication process: GlobalFoundries 14 LP.
Branding and Model Cores
(threads) 		Thermal solution Clock rate (GHz) L3 cache
(total) 		TDP Core
config[i]		 Release
date
Base PBO
1–2
(≥3) 		XFR[94]
1–2
Ryzen 7 1800X 8 (16) Wraith Max (OEM only) 3.6 4.0
(3.7) 		4.1 16 MB 95 W 2 × 4 March 2, 2017
PRO 1700X Wraith Spire 3.4 3.8
(3.5) 		3.9 June 29, 2017
1700X Wraith Max (OEM only) March 2, 2017
PRO 1700 Wraith Spire 3.0 3.7
(3.2) 		3.75 65 W June 29, 2017
1700 Wraith Spire LED (retail)
Wraith Spire (OEM) 		March 2, 2017
Ryzen 5 1600X 6 (12) Wraith Max (OEM only) 3.6 4.0
(3.7) 		4.1 95 W 2 × 3 April 11, 2017
PRO 1600 Wraith Spire 3.2 3.6
(3.4) 		3.7 65 W June 29, 2017
1600 April 11, 2017
1500X 4 (8) 3.5 3.7
(3.6) 		3.9 2 × 2
PRO 1500 June 29, 2017
1400 Wraith Stealth 3.2 3.4
(3.4) 		3.45 8 MB April 11, 2017
Ryzen 3 1300X 4 (4) 3.5 3.7
(3.5) 		3.9 July 27, 2017
PRO 1300 Wraith Spire June 29, 2017
PRO 1200 3.1 3.4
(3.1) 		3.45
1200 Wraith Stealth July 27, 2017
  1. ^ Core Complexes (CCX) × cores per CCX


Common features of Ryzen 1000 HEDT CPUs:

  • Socket: TR4.
  • All the CPUs support DDR4-2666 in quad-channel mode.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • No integrated graphics.
  • Node/fabrication process: GlobalFoundries 14LP.
Branding and Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i]		 Release
date 		MSRP
Base PBO
1–4
(≥5) 		XFR[94]
1–2
Ryzen
Threadripper 		1950X 16 (32) 3.4 4.0
(3.7) 		4.2 32 MB 180 W 2 × CCD[ii] 4 × 4 Aug 31, 2017 US $999
1920X 12 (24) 3.5 4 × 3 US $799
1900X 8 (16) 3.8 4.0
(3.9) 		16 MB 2 × 4 US $549
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ Processor package actually contains two additional inactive dies to provide structural support to the integrated heat spreader.
 
Ryzen 5 1600 CPU on a motherboard
 
Threadripper 1950X TR4 in socket

Desktop APUs edit

Ryzen APUs are identified by either the G or GE suffix in their name.

 
Die shot of an AMD 2200G APU
Model Release date
& price 		Fab Thermal Solution CPU GPU Socket PCIe lanes DDR4
memory
support 		TDP
(W)
Cores
(threads) 		Clock rate (GHz) Cache Model Config[i] Clock
(GHz) 		Processing
power
(GFLOPS)[ii]
Base Boost L1 L2 L3
Athlon 200GE[95] September 6, 2018
US $55 		GloFo
14LP 		AMD 65W thermal solution 2 (4) 3.2 — 64 KB inst.
32 KB data
per core 		512 KB
per core 		4 MB Vega 3 192:12:4
3 CU 		1.0 384 AM4 16 (8+4+4) 2667
dual-channel 		35
Athlon Pro 200GE[96] September 6, 2018
OEM 		OEM
Athlon 220GE[97] December 21, 2018
US $65 		AMD 65W thermal solution 3.4
Athlon 240GE[98] December 21, 2018
US $75 		3.5
Athlon 3000G[99] November 19, 2019
US $49 		1.1 424.4
Athlon 300GE[100] July 7, 2019
OEM 		OEM 3.4
Athlon Silver 3050GE[101] July 21, 2020
OEM
Ryzen 3 Pro 2100GE[102] c. 2019

OEM

3.2 ? ? 2933
dual-channel
Ryzen 3 2200GE[103] April 19, 2018
OEM 		4 (4) 3.2 3.6 Vega 8 512:32:16
8 CU 		1126
Ryzen 3 Pro 2200GE[104] May 10, 2018
OEM
Ryzen 3 2200G February 12, 2018
US $99 		Wraith Stealth 3.5 3.7 45–
65
Ryzen 3 Pro 2200G[105] May 10, 2018
OEM 		OEM
Ryzen 5 2400GE[106] April 19, 2018
OEM 		4 (8) 3.2 3.8 RX Vega 11 704:44:16
11 CU 		1.25 1760 35
Ryzen 5 Pro 2400GE[107] May 10, 2018
OEM
Ryzen 5 2400G[108] February 12, 2018[109][110]
US $169 		Wraith Stealth 3.6 3.9 45–
65
Ryzen 5 Pro 2400G[111] May 10, 2018
OEM 		OEM
  1. ^ Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
  2. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Mobile APUs edit

Model Release
date 		Fab CPU GPU Socket PCIe
lanes 		Memory
support 		TDP
Cores
(threads) 		Clock rate (GHz) Cache Model Config[i] Clock
(MHz) 		Processing
power
(GFLOPS)[ii]
Base Boost L1 L2 L3
Athlon Pro 200U 2019 GloFo
14LP 		2 (4) 2.3 3.2 64 KB inst.
32 KB data
per core 		512 KB
per core 		4 MB Radeon Vega 3 192:12:4
3 CU 		1000 384 FP5 12 (8+4) DDR4-2400
dual-channel 		12–25 W
Athlon 300U Jan 6, 2019 2.4 3.3
Ryzen 3 2200U Jan 8, 2018 2.5 3.4 1100 422.4
Ryzen 3 3200U Jan 6, 2019 2.6 3.5 1200 460.8
Ryzen 3 2300U Jan 8, 2018 4 (4) 2.0 3.4 Radeon Vega 6 384:24:8
6 CU 		1100 844.8
Ryzen 3 Pro 2300U May 15, 2018
Ryzen 5 2500U Oct 26, 2017 4 (8) 3.6 Radeon Vega 8 512:32:16
8 CU 		1126.4
Ryzen 5 Pro 2500U May 15, 2018
Ryzen 5 2600H Sep 10, 2018 3.2 DDR4-3200
dual-channel 		35–54 W
Ryzen 7 2700U Oct 26, 2017 2.2 3.8 Radeon RX Vega 10 640:40:16
10 CU 		1300 1664 DDR4-2400
dual-channel 		12–25 W
Ryzen 7 Pro 2700U May 15, 2018 Radeon Vega 10
Ryzen 7 2800H Sep 10, 2018 3.3 Radeon RX Vega 11 704:44:16
11 CU 		1830.4 DDR4-3200
dual-channel 		35–54 W
  1. ^ Unified shaders : Texture mapping units : Render output units and Compute units (CU)
  2. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Ultra-mobile APUs edit

Dalí edit

Model Release
date 		Fab CPU GPU Socket PCIe
lanes 		Memory
support 		TDP Part number
Cores
(threads) 		Clock rate (GHz) Cache Model Config[a] Clock
(GHz) 		Processing
power
(GFLOPS)[b]
Base Boost L1 L2 L3
AMD 3020e Jan 6, 2020 14 nm 2 (2) 1.2 2.6 64 KB inst.
32 KB data
per core 		512 KB
per core 		4 MB Radeon
Graphics
(Vega) 		192:12:4
3 CU 		1.0 384 FP5 12 (8+4) DDR4-2400
dual-channel 		6 W YM3020C7T2OFG
Athlon PRO 3045B Q1 2021 2.3 3.2 128:8:4
2 CU 		1.1 281.6 15 W YM3045C4T2OFG
Athlon Silver 3050U Jan 6, 2020 YM3050C4T2OFG
Athlon Silver 3050C Sep 22, 2020 YM305CC4T2OFG
Athlon Silver 3050e Jan 6, 2020 2 (4) 1.4 2.8 192:12:4
3 CU[112]		 1.0 384 6 W YM3050C7T2OFG
Athlon PRO 3145B Q1 2021 2.4 3.3 15 W YM3145C4T2OFG
Athlon Gold 3150U Jan 6, 2020 YM3150C4T2OFG
Athlon Gold 3150C Sep 22, 2020 YM315CC4T2OFG
Ryzen 3 3250U Jan 6, 2020 2.6 3.5 1.2 460.8 YM3250C4T2OFG
Ryzen 3 3250C Sep 22, 2020 YM325CC4T2OFG
  1. ^ Unified shaders : Texture mapping units : Render output units and Compute units (CU)
  2. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Pollock edit

Model Release
date 		Fab CPU GPU Socket PCIe
lanes 		Memory
support 		TDP Part number
Cores
(threads) 		Clock rate (GHz) Cache Model Config[a] Clock
(GHz) 		Processing
power
(GFLOPS)[b]
Base Boost L1 L2 L3
AMD 3015e Jul 6, 2020 14 nm 2 (4) 1.2 2.3 64 KB inst.
32 KB data
per core 		512 KB
per core 		4 MB Radeon
Graphics
(Vega) 		192:12:4
3 CU 		0.6 230.4 FT5 12 (8+4) DDR4-1600
single-channel 		6 W AM3015BRP2OFJ
AMD 3015Ce Apr 29, 2021 AM301CBRP2OFJ
  1. ^ Unified shaders : Texture mapping units : Render output units and Compute units (CU)
  2. ^ Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Embedded processors edit

V1000 edit

In February 2018, AMD announced the V1000 series of embedded Zen+Vega APUs with four SKUs.[113]

Model Release
date 		Fab CPU GPU Memory
support 		TDP Junction
temp.
range
(°C)
Cores
(threads) 		Clock rate (GHz) Cache Model Config[i] Clock
(GHz) 		Processing
power
(GFLOPS)[ii]
Base Boost L1 L2 L3
V1202B February 2018 GloFo
14LP 		2 (4) 2.3 3.2 64 KB inst.
32 KB data
per core 		512 KB
per core 		4 MB Vega 3 192:12:16
3 CU 		1.0 384 DDR4-2400
dual-channel 		12–25 W 0–105
V1404I December 2018 4 (8) 2.0 3.6 Vega 8 512:32:16
8 CU 		1.1 1126.4 -40–105
V1500B 2.2 — — 0–105
V1605B February 2018 2.0 3.6 Vega 8 512:32:16
8 CU 		1.1 1126.4
V1756B 3.25 DDR4-3200
dual-channel 		35–54 W
V1780B December 2018 3.35 —
V1807B February 2018 3.8 Vega 11 704:44:16
11 CU 		1.3 1830.4
  1. ^ Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
  2. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

R1000 edit

In 2019, AMD announced the R1000 series of embedded Zen+Vega APUs.

Model Release
date 		Fab CPU GPU Memory
support 		TDP
Cores
(threads) 		Clock rate (GHz) Cache Model Config[i] Clock
(GHz) 		Processing
power
(GFLOPS)[ii]
Base Boost L1 L2 L3
R1102G February 25, 2020 GloFo
14LP 		2 (2) 1.2 2.6 64 KB inst.
32 KB data
per core 		512 KB
per core 		4 MB Vega 3 192:12:4
3 CU 		1.0 384 DDR4-2400
single-channel 		6 W
R1305G 2 (4) 1.5 2.8 DDR4-2400
dual-channel 		8-10 W
R1505G April 16, 2019 2.4 3.3 12–25 W
R1606G 2.6 3.5 1.2 460.8
  1. ^ Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
  2. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Server processors edit

Main article: Epyc
 
Epyc

AMD announced in March 2017 that it would release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform include 1- and 2-socket systems. The CPUs in multi-processor configurations communicate via AMD's Infinity Fabric.[114] Each chip supports eight channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.[115] AMD officially revealed Naples under the brand name Epyc in May 2017.[116]

On June 20, 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.[117] Common features of EPYC 7001 series CPUs:

  • Socket: SP3.
  • All the CPUs support ECC DDR4-2666 in octa-channel mode (7251 supports only DDR4-2400).
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 128 PCIe 3.0 lanes.
  • Fabrication process: GlobalFoundries 14 nm.
Brand Model[i] Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[ii]		 Release
date 		Price
(1kU) 		Embedded
option[iii]
Base Boost
All–core Max
EPYC 7251[118][119] 8 (16) 2.1 2.9 2.9 32 MB 120 W 4 × CCD 8 × 1 Jun 2017[120] US $475 Yes
7261[118][121] 2.5 64 MB 155/170 W Jun 2018[122] US $570 Yes
7281[118][119] 16 (32) 2.1 2.7 2.7 32 MB 8 × 2 Jun 2017[120] US $650 Yes
7301[118][119] 2.2 64 MB US $800 Yes
7351P[118][119] 2.4 2.9 2.9 US $750 735P
7351[118][119] US $1100 Yes
7371[118][123] 3.1 3.6 3.8 200 W Nov 2018[124] US $1550 Yes
7401P[118][119] 24 (48) 2.0 2.8 3.0 155/170 W 8 × 3 Jun 2017[120] US $1075 740P
7401[118][119] US $1850 Yes
7451[118][119] 2.3 2.9 3.2 180 W US $2400 Yes
7501[118][119] 32 (64) 2.0 2.6 3.0 155/170 W 8 × 4 US $3400 Yes
7551P[118][119] 2.55 180 W US $2100 755P
7551[118][119] US $3400 Yes
7571[125][126] 2.2 3.0 200 W Nov 2018 OEM/AWS Un­known
7601[118][119] 2.7 3.2 180 W Jun 2017[120] US $4200 Yes
  1. ^ Models with "P" suffixes are uniprocessors, only available as single socket configuration.
  2. ^ Core Complexes (CCX) × cores per CCX
  3. ^ EPYC Embedded 7001 series models have identical specifications as EPYC 7001 series.

Embedded server processors edit

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.[127]Common features of EPYC Embedded 3000 series CPUs:

  • Socket: SP4 (31xx and 32xx models use SP4r2 package).
  • All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
  • L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
  • L2 cache: 512 KB per core.
  • All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
  • Fabrication process: GlobalFoundries 14 nm.
Brand Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i]		 Release
date
Base Boost
All-core Max
EPYC
Embedded 		3101[128] 4 (4) 2.1 2.9 2.9 8 MB 35 W 1 x CCD 1 × 4 Feb 2018
3151[128] 4 (8) 2.7 16 MB 45 W 2 × 2
3201[128] 8 (8) 1.5 3.1 3.1 30 W 2 × 4
3251[128] 8 (16) 2.5 55 W
3255[129] 25–55 W Dec 2018
3301[128] 12 (12) 2.0 2.15 3.0 32 MB 65 W 2 x CCD 4 × 3 Feb 2018
3351[128] 12 (24) 1.9 2.75 60–80 W
3401[128] 16 (16) 1.85 2.25 85 W 4 × 4
3451[128] 16 (32) 2.15 2.45 80–100 W
  1. ^ Core Complexes (CCX) × cores per CCX

See also edit

 
Wikimedia Commons has media related to Zen microarchitecture.

References edit

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External links edit

  • Ryzen Processors – AMD

November 19, 2023
first, generation, this, article, about, first, generation, microarchitecture, architecture, family, microarchitecture, codename, first, iteration, family, computer, processor, microarchitectures, same, name, from, first, used, with, their, ryzen, series, cpus. This article is about the first generation of the Zen microarchitecture For the CPU architecture family see Zen microarchitecture Zen is the codename for the first iteration in a family of computer processor microarchitectures of the same name from AMD It was first used with their Ryzen series of CPUs in February 2017 3 The first Zen based preview system was demonstrated at E3 2016 and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016 The first Zen based CPUs codenamed Summit Ridge reached the market in early March 2017 Zen derived Epyc server processors launched in June 2017 10 and Zen based APUs arrived in November 2017 11 AMD ZenThe logo for the Zen microarchitecture is a closed ensōGeneral informationLaunchedMarch 2 2017 6 years ago March 2 2017 1 Designed byAMDCommon manufacturer s GlobalFoundries 2 CPUID codeFamily 17hCacheL1 cache64 KB instruction 32 KB data per coreL2 cache512 KB per coreL3 cache8 MB per quad core CCX APU 4 MB Architecture and classificationInstruction setAMD64 x86 64 Physical specificationsTransistors14 nm FinFET 2 Cores2 4 essential 4 8 mainstream 8 16 enthusiast 3 4 5 6 Up to 32 server 3 7 Socket s Socket AM4 8 Socket TR4Socket SP3Products models variantsProduct code name s Summit Ridge Desktop Whitehaven HEDT Raven Ridge APU Embedded Naples Server CPU Snowy Owl Server APU 9 Brand name s RyzenRyzen ThreadripperEpycAthlonHistoryPredecessor s Excavator 4th gen Successor s Zen Support statusSupportedZen is a clean sheet design that differs from AMD s previous long standing Bulldozer architecture Zen based processors use a 14 nm FinFET process are reportedly more energy efficient and can execute significantly more instructions per cycle SMT has been introduced allowing each core to run two threads The cache system has also been redesigned making the L1 cache write back Zen processors use three different sockets desktop and mobile Ryzen chips use the AM4 socket bringing DDR4 support the high end desktop Zen based Threadripper chips support quad channel DDR4 RAM and offer 64 PCIe 3 0 lanes vs 24 lanes using the TR4 socket 12 13 and Epyc server processors offer 128 PCI 3 0 lanes and octa channel DDR4 using the SP3 socket Zen is based on a SoC design 14 The memory controller and the PCIe SATA and USB controllers are incorporated into the same chip s as the processor cores This has advantages in bandwidth and power at the expense of chip complexity and die area 15 This SoC design allows the Zen microarchitecture to scale from laptops and small form factor mini PCs to high end desktops and servers By 2020 260 million Zen cores have already been shipped by AMD 16 Contents 1 Design 2 History and development 3 Advantages over predecessors 3 1 Manufacturing process 3 2 Performance 3 3 Memory 3 4 Power consumption and heat output 3 5 Enhanced security and virtualization support 3 6 Connectivity 4 Features 4 1 CPUs 4 2 APUs 5 Products 5 1 Desktop processors 5 2 Desktop APUs 5 3 Mobile APUs 5 4 Ultra mobile APUs 5 4 1 Dali 5 4 2 Pollock 5 5 Embedded processors 5 5 1 V1000 5 5 2 R1000 5 6 Server processors 5 7 Embedded server processors 6 See also 7 References 8 External linksDesign edit nbsp A highly simplified illustration of the Zen microarchitecture a core has a total of 512 KB of L2 cache nbsp Ryzen 3 1200 Die Shot nbsp Photomontage of a delidded Zen CPU with an etched die nbsp A delidded AMD EPYC processor used in servers The four dies are similar to the ones used in mainstream processors All EPYC processors contain four dies to provide structural support to the IHS Integrated Heat Spreader 17 18 19 nbsp A delidded AMD Athlon 3000G APU based on the Zen architecture The die is physically smaller than those on mainstream Zen processors nbsp Die shot of an AMD Athlon 3000GAccording to AMD the main focus of Zen is on increasing per core performance 20 21 22 New or improved features include 23 The L1 cache has been changed from write through to write back allowing for lower latency and higher bandwidth SMT simultaneous multithreading architecture allows for two threads per core a departure from the CMT clustered multi thread design used in the previous Bulldozer architecture This is a feature previously offered in some IBM Intel and Oracle processors 24 A fundamental building block for all Zen based CPUs is the Core Complex CCX consisting of four cores and their associated caches Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric 25 Processors with non multiple of four core counts have some cores disabled Four ALUs two AGUs load store units and two floating point units per core 26 Newly introduced large micro operation cache 27 Each SMT core can dispatch up to six micro ops per cycle a combination of 6 integer micro ops and 4 floating point micro ops per cycle 28 29 Close to 2 faster L1 and L2 bandwidth with total L3 cache bandwidth up 5 Clock gating Larger retire load and store queues Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture 30 something that has been compared to a neural network by AMD engineer Mike Clark 31 The branch predictor is decoupled from the fetch stage A dedicated stack engine for modifying the stack pointer similar to that of Intel Haswell and Broadwell processors 32 Move elimination a method that reduces physical data movement to reduce power consumption Binary compatibility with Intel s Skylake excluding VT x and private MSRs RDSEED support a set of high performance hardware random number generator instructions introduced in Broadwell 33 Support for the SMAP SMEP XSAVEC XSAVES XRSTORS and CLFLUSHOPT instructions 33 ADX support SHA support CLZERO instruction for clearing a cache line 33 Useful for handling ECC related Machine check exceptions PTE page table entry coalescing which combines 4 kB page tables into 32 kB page size Pure Power more accurate power monitoring sensors 34 Support for intel style running average power limit RAPL measurement 35 Smart Prefetch Precision Boost eXtended Frequency Range XFR an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency 36 This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do It is a multi year project with a really large team It s like a marathon effort with some sprints in the middle The team is working very hard but they can see the finish line I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation Suzanne Plummer Zen team leader on September 19th 2015 37 The Zen architecture is built on a 14 nanometer FinFET process subcontracted to GlobalFoundries 38 which in turn licenses its 14 nm process from Samsung Electronics 39 This gives greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs respectively 40 The Summit Ridge Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP thermal design power 40 While newer roadmaps don t confirm the TDP for desktop products they suggest a range for low power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance oriented mobile products with up to four Zen cores 41 Each Zen core can decode four instructions per clock cycle and includes a micro op cache which feeds two schedulers one each for the integer and floating point segments 42 43 Each core has two address generation units four integer units and four floating point units Two of the floating point units are adders and two are multiply adders However using multiply add operations may prevent simultaneous add operation in one of the adder units 44 There are also improvements in the branch predictor The L1 cache size is 64 KB for instructions per core and 32 KB for data per core The L2 cache size 512 KB per core and the L3 is 1 2 MB per core L3 caches offer 5 the bandwidth of previous AMD designs History and development editAMD began planning the Zen microarchitecture shortly after re hiring Jim Keller in August 2012 45 AMD formally revealed Zen in 2015 The team in charge of Zen was led by Keller who left in September 2015 after a 3 year tenure and Zen Team Leader Suzanne Plummer 46 47 The Chief Architect of Zen was AMD Senior Fellow Michael Clark 48 49 50 Zen was originally planned for 2017 following the ARM64 based K12 sister core but on AMD s 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design to allow it to enter the market within the 2016 timeframe 8 with the release of the first Zen based processors expected for October 2016 51 In November 2015 a source inside AMD reported that Zen microprocessors had been tested and met all expectations with no significant bottlenecks found 2 52 In December 2015 it was rumored that Samsung may have been contracted as a fabricator for AMD s 14 nm FinFET processors including both Zen and AMD s then upcoming Polaris GPU architecture 53 This was clarified by AMD s July 2016 announcement that products had been successfully produced on Samsung s 14 nm FinFET process 54 AMD stated Samsung would be used if needed arguing this would reduce risk for AMD by decreasing dependence on any one foundry In December 2019 AMD started putting out first generation Ryzen products built using the second generation Zen architecture 55 Advantages over predecessors editManufacturing process edit Processors based on Zen use 14 nm FinFET silicon 56 These processors are reportedly produced at GlobalFoundries 57 Prior to Zen AMD s smallest process size was 28 nm as utilized by their Steamroller and Excavator microarchitectures 58 59 The immediate competition Intel s Skylake and Kaby Lake microarchitecture are also fabricated on 14 nm FinFET 60 though Intel planned to begin the release of 10 nm parts later in 2017 61 Intel was unable to reach this goal and in 2021 only mobile chips have been produced with the 10nm process In comparison to Intel s 14 nm FinFET AMD claimed in February 2017 the Zen cores would be 10 smaller 62 Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019 63 For identical designs these die shrinks would use less current and power at the same frequency or voltage As CPUs are usually power limited typically up to 125 W or 45 W for mobile smaller transistors allow for either lower power at the same frequency or higher frequency at the same power 64 Performance edit One of Zen s major goals in 2016 was to focus on performance per core and it was targeting a 40 improvement in instructions per cycle IPC over its predecessor 65 Excavator in comparison offered 4 15 improvement over previous architectures 66 67 AMD announced the final Zen microarchitecture actually achieved 52 improvement in IPC over Excavator 68 The inclusion of SMT also allows each core to process up to two threads increasing processing throughput by better use of available resources The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage 69 This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling AMD has demonstrated an 8 core 16 thread Zen processor outperforming an equally clocked Intel Broadwell E processor in Blender rendering 3 9 and HandBrake benchmarks 69 Zen supports AVX2 but it requires two clock cycles to complete each AVX2 instruction compared to Intel s one 70 71 This difference was corrected in Zen 2 Memory edit Zen supports DDR4 memory up to eight channels 72 and ECC 73 Pre release reports stated APUs using the Zen architecture would also support High Bandwidth Memory HBM 74 However the first demonstrated APU did not use HBM 75 Previous APUs from AMD relied on shared memory for both the GPU and the CPU Power consumption and heat output edit Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non FinFET predecessors for equivalent designs or be more computationally powerful at equivalent heat output power consumption Zen also uses clock gating 43 reducing the frequency of underutilized portions of the core to save power This comes from AMD s SenseMI technology using sensors across the chip to dynamically scale frequency and voltage 69 Enhanced security and virtualization support edit Zen added support for AMD s Secure Memory Encryption SME and AMD s Secure Encrypted Virtualization SEV Secure Memory Encryption is real time memory encryption done per page table entry Encryption occurs on a hardware AES engine and keys are managed by the onboard Security Processor ARM Cortex A5 at boot time to encrypt each page allowing any DDR4 memory including non volatile varieties to be encrypted AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks 76 77 SME can be used to mark individual pages of memory as encrypted through the page tables A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR Once enabled page table entries will determine how the memory is accessed If a page table entry has the memory encryption mask set then that memory will be accessed as encrypted memory The memory encryption mask as well as other related information is determined from settings returned through the same CPUID function that identifies the presence of the feature 78 The Secure Encrypted Virtualization SEV feature allows the memory contents of a virtual machine VM to be transparently encrypted with a key unique to the guest VM The memory controller contains a high performance encryption engine which can be programmed with multiple keys for use by different VMs in the system The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks 79 Connectivity edit Incorporating much of the southbridge into the SoC the Zen CPU includes SATA USB and PCI Express NVMe links 80 81 This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections and support for AMD s Crossfire and Nvidia s SLI 82 AMD in announcing its Radeon Instinct line argued that the upcoming Zen based Naples server CPU would be particularly suited for building deep learning systems 83 84 The 128 85 PCIe lanes per Naples CPU allows for eight Instinct cards to connect at PCIe x16 to a single CPU This compares favorably to the Intel Xeon line with only 40 citation needed PCIe lanes Features editCPUs edit This section is empty You can help by adding to it March 2023 APUs edit APU features tableProducts editThe Zen architecture is used in the current generation desktop Ryzen CPUs It is also in Epyc server processors successor of Opteron processors and APUs 74 unreliable source 86 87 The first desktop processors without graphics processing units codenamed Summit Ridge were initially expected to start selling at the end of 2016 according to an AMD roadmap with the first mobile and desktop processors of the AMD Accelerated Processing Unit type codenamed Raven Ridge following in late 2017 88 AMD officially delayed Zen until Q1 of 2017 In August 2016 an early demonstration of the architecture showed an 8 core 16 thread engineering sample CPU at 3 0 GHz 9 In December 2016 AMD officially announced the desktop CPU line under the Ryzen brand for release in Q1 2017 It also confirmed Server processors would be released in Q2 2017 and mobile APUs in H2 2017 89 On March 2 2017 AMD officially launched the first Zen architecture based octacore Ryzen desktop CPUs The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance per watt benefits over the previous K15h Piledriver architecture 90 91 The octacore Ryzen desktop CPUs demonstrated performance per watt comparable to Intel s Broadwell octacore CPUs 92 93 In March 2017 AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture The CPU codenamed Naples was configured as a dual socket server platform with each CPU having 32 cores 64 threads 3 9 Desktop processors edit Main article Ryzen Common features of Ryzen 1000 desktop CPUs Socket AM4 All the CPUs support DDR4 2666 in dual channel mode L1 cache 96 KB 32 KB data 64 KB instruction per core L2 cache 512 KB per core All the CPUs support 24 PCIe 3 0 lanes 4 of the lanes are reserved as link to the chipset No integrated graphics Node fabrication process GlobalFoundries 14 LP Branding and Model Cores threads Thermal solution Clock rate GHz L3 cache total TDP Coreconfig i ReleasedateBase PBO1 2 3 XFR 94 1 2Ryzen 7 1800X 8 16 Wraith Max OEM only 3 6 4 0 3 7 4 1 16 MB 95 W 2 4 March 2 2017PRO 1700X Wraith Spire 3 4 3 8 3 5 3 9 June 29 20171700X Wraith Max OEM only March 2 2017PRO 1700 Wraith Spire 3 0 3 7 3 2 3 75 65 W June 29 20171700 Wraith Spire LED retail Wraith Spire OEM March 2 2017Ryzen 5 1600X 6 12 Wraith Max OEM only 3 6 4 0 3 7 4 1 95 W 2 3 April 11 2017PRO 1600 Wraith Spire 3 2 3 6 3 4 3 7 65 W June 29 20171600 April 11 20171500X 4 8 3 5 3 7 3 6 3 9 2 2PRO 1500 June 29 20171400 Wraith Stealth 3 2 3 4 3 4 3 45 8 MB April 11 2017Ryzen 3 1300X 4 4 3 5 3 7 3 5 3 9 July 27 2017PRO 1300 Wraith Spire June 29 2017PRO 1200 3 1 3 4 3 1 3 451200 Wraith Stealth July 27 2017vte Core Complexes CCX cores per CCX Common features of Ryzen 1000 HEDT CPUs Socket TR4 All the CPUs support DDR4 2666 in quad channel mode L1 cache 96 KB 32 KB data 64 KB instruction per core L2 cache 512 KB per core All the CPUs support 64 PCIe 3 0 lanes 4 of the lanes are reserved as link to the chipset No integrated graphics Node fabrication process GlobalFoundries 14LP Branding and Model Cores threads Clock rate GHz L3 cache total TDP Chiplets Coreconfig i Releasedate MSRPBase PBO1 4 5 XFR 94 1 2RyzenThreadripper 1950X 16 32 3 4 4 0 3 7 4 2 32 MB 180 W 2 CCD ii 4 4 Aug 31 2017 US 9991920X 12 24 3 5 4 3 US 7991900X 8 16 3 8 4 0 3 9 16 MB 2 4 US 549vte Core Complexes CCX cores per CCX Processor package actually contains two additional inactive dies to provide structural support to the integrated heat spreader nbsp Ryzen 5 1600 CPU on a motherboard nbsp Threadripper 1950X TR4 in socketDesktop APUs edit Ryzen APUs are identified by either the G or GE suffix in their name nbsp Die shot of an AMD 2200G APUModel Release date amp price Fab Thermal Solution CPU GPU Socket PCIe lanes DDR4memorysupport TDP W Cores threads Clock rate GHz Cache Model Config i Clock GHz Processingpower GFLOPS ii Base Boost L1 L2 L3Athlon 200GE 95 September 6 2018US 55 GloFo14LP AMD 65W thermal solution 2 4 3 2 64 KB inst 32 KB dataper core 512 KBper core 4 MB Vega 3 192 12 43 CU 1 0 384 AM4 16 8 4 4 2667dual channel 35Athlon Pro 200GE 96 September 6 2018OEM OEMAthlon 220GE 97 December 21 2018US 65 AMD 65W thermal solution 3 4Athlon 240GE 98 December 21 2018US 75 3 5Athlon 3000G 99 November 19 2019US 49 1 1 424 4Athlon 300GE 100 July 7 2019OEM OEM 3 4Athlon Silver 3050GE 101 July 21 2020OEMRyzen 3 Pro 2100GE 102 c 2019 OEM 3 2 2933dual channelRyzen 3 2200GE 103 April 19 2018OEM 4 4 3 2 3 6 Vega 8 512 32 168 CU 1126Ryzen 3 Pro 2200GE 104 May 10 2018OEMRyzen 3 2200G February 12 2018US 99 Wraith Stealth 3 5 3 7 45 65Ryzen 3 Pro 2200G 105 May 10 2018OEM OEMRyzen 5 2400GE 106 April 19 2018OEM 4 8 3 2 3 8 RX Vega 11 704 44 1611 CU 1 25 1760 35Ryzen 5 Pro 2400GE 107 May 10 2018OEMRyzen 5 2400G 108 February 12 2018 109 110 US 169 Wraith Stealth 3 6 3 9 45 65Ryzen 5 Pro 2400G 111 May 10 2018OEM OEMvte Unified Shaders Texture Mapping Units Render Output Units and Compute Units CU Single precision performance is calculated from the base or boost core clock speed based on a FMA operation Mobile APUs edit Model Releasedate Fab CPU GPU Socket PCIelanes Memorysupport TDPCores threads Clock rate GHz Cache Model Config i Clock MHz Processingpower GFLOPS ii Base Boost L1 L2 L3Athlon Pro 200U 2019 GloFo14LP 2 4 2 3 3 2 64 KB inst 32 KB dataper core 512 KBper core 4 MB Radeon Vega 3 192 12 43 CU 1000 384 FP5 12 8 4 DDR4 2400dual channel 12 25 WAthlon 300U Jan 6 2019 2 4 3 3Ryzen 3 2200U Jan 8 2018 2 5 3 4 1100 422 4Ryzen 3 3200U Jan 6 2019 2 6 3 5 1200 460 8Ryzen 3 2300U Jan 8 2018 4 4 2 0 3 4 Radeon Vega 6 384 24 86 CU 1100 844 8Ryzen 3 Pro 2300U May 15 2018Ryzen 5 2500U Oct 26 2017 4 8 3 6 Radeon Vega 8 512 32 168 CU 1126 4Ryzen 5 Pro 2500U May 15 2018Ryzen 5 2600H Sep 10 2018 3 2 DDR4 3200dual channel 35 54 WRyzen 7 2700U Oct 26 2017 2 2 3 8 Radeon RX Vega 10 640 40 1610 CU 1300 1664 DDR4 2400dual channel 12 25 WRyzen 7 Pro 2700U May 15 2018 Radeon Vega 10Ryzen 7 2800H Sep 10 2018 3 3 Radeon RX Vega 11 704 44 1611 CU 1830 4 DDR4 3200dual channel 35 54 Wvte Unified shaders Texture mapping units Render output units and Compute units CU Single precision performance is calculated from the base or boost core clock speed based on a FMA operation Ultra mobile APUs edit Dali edit Model Releasedate Fab CPU GPU Socket PCIelanes Memorysupport TDP Part numberCores threads Clock rate GHz Cache Model Config a Clock GHz Processingpower GFLOPS b Base Boost L1 L2 L3AMD 3020e Jan 6 2020 14 nm 2 2 1 2 2 6 64 KB inst 32 KB dataper core 512 KBper core 4 MB RadeonGraphics Vega 192 12 43 CU 1 0 384 FP5 12 8 4 DDR4 2400dual channel 6 W YM3020C7T2OFGAthlon PRO 3045B Q1 2021 2 3 3 2 128 8 42 CU 1 1 281 6 15 W YM3045C4T2OFGAthlon Silver 3050U Jan 6 2020 YM3050C4T2OFGAthlon Silver 3050C Sep 22 2020 YM305CC4T2OFGAthlon Silver 3050e Jan 6 2020 2 4 1 4 2 8 192 12 43 CU 112 1 0 384 6 W YM3050C7T2OFGAthlon PRO 3145B Q1 2021 2 4 3 3 15 W YM3145C4T2OFGAthlon Gold 3150U Jan 6 2020 YM3150C4T2OFGAthlon Gold 3150C Sep 22 2020 YM315CC4T2OFGRyzen 3 3250U Jan 6 2020 2 6 3 5 1 2 460 8 YM3250C4T2OFGRyzen 3 3250C Sep 22 2020 YM325CC4T2OFGvte Unified shaders Texture mapping units Render output units and Compute units CU Single precision performance is calculated from the base or boost core clock speed based on a FMA operation Pollock edit Model Releasedate Fab CPU GPU Socket PCIelanes Memorysupport TDP Part numberCores threads Clock rate GHz Cache Model Config a Clock GHz Processingpower GFLOPS b Base Boost L1 L2 L3AMD 3015e Jul 6 2020 14 nm 2 4 1 2 2 3 64 KB inst 32 KB dataper core 512 KBper core 4 MB RadeonGraphics Vega 192 12 43 CU 0 6 230 4 FT5 12 8 4 DDR4 1600single channel 6 W AM3015BRP2OFJAMD 3015Ce Apr 29 2021 AM301CBRP2OFJvte Unified shaders Texture mapping units Render output units and Compute units CU Single precision performance is calculated from the base or boost core clock speed based on a FMA operation Embedded processors edit V1000 edit In February 2018 AMD announced the V1000 series of embedded Zen Vega APUs with four SKUs 113 Model Releasedate Fab CPU GPU Memorysupport TDP Junctiontemp range C Cores threads Clock rate GHz Cache Model Config i Clock GHz Processingpower GFLOPS ii Base Boost L1 L2 L3V1202B February 2018 GloFo14LP 2 4 2 3 3 2 64 KB inst 32 KB dataper core 512 KBper core 4 MB Vega 3 192 12 163 CU 1 0 384 DDR4 2400dual channel 12 25 W 0 105V1404I December 2018 4 8 2 0 3 6 Vega 8 512 32 168 CU 1 1 1126 4 40 105V1500B 2 2 0 105V1605B February 2018 2 0 3 6 Vega 8 512 32 168 CU 1 1 1126 4V1756B 3 25 DDR4 3200dual channel 35 54 WV1780B December 2018 3 35 V1807B February 2018 3 8 Vega 11 704 44 1611 CU 1 3 1830 4vte Unified Shaders Texture Mapping Units Render Output Units and Compute Units CU Single precision performance is calculated from the base or boost core clock speed based on a FMA operation R1000 edit In 2019 AMD announced the R1000 series of embedded Zen Vega APUs Model Releasedate Fab CPU GPU Memorysupport TDPCores threads Clock rate GHz Cache Model Config i Clock GHz Processingpower GFLOPS ii Base Boost L1 L2 L3R1102G February 25 2020 GloFo14LP 2 2 1 2 2 6 64 KB inst 32 KB dataper core 512 KBper core 4 MB Vega 3 192 12 43 CU 1 0 384 DDR4 2400single channel 6 WR1305G 2 4 1 5 2 8 DDR4 2400dual channel 8 10 WR1505G April 16 2019 2 4 3 3 12 25 WR1606G 2 6 3 5 1 2 460 8vte Unified Shaders Texture Mapping Units Render Output Units and Compute Units CU Single precision performance is calculated from the base or boost core clock speed based on a FMA operation Server processors edit Main article Epyc nbsp EpycAMD announced in March 2017 that it would release a server platform based on Zen codenamed Naples in the second quarter of the year The platform include 1 and 2 socket systems The CPUs in multi processor configurations communicate via AMD s Infinity Fabric 114 Each chip supports eight channels of memory and 128 PCIe 3 0 lanes of which 64 lanes are used for CPU to CPU communication through Infinity Fabric when installed in a dual processor configuration 115 AMD officially revealed Naples under the brand name Epyc in May 2017 116 On June 20 2017 AMD officially released the Epyc 7000 series CPUs at a launch event in Austin Texas 117 Common features of EPYC 7001 series CPUs Socket SP3 All the CPUs support ECC DDR4 2666 in octa channel mode 7251 supports only DDR4 2400 L1 cache 96 KB 32 KB data 64 KB instruction per core L2 cache 512 KB per core All the CPUs support 128 PCIe 3 0 lanes Fabrication process GlobalFoundries 14 nm Brand Model i Cores threads Clock rate GHz L3 cache total TDP Chiplets Coreconfig ii Releasedate Price 1kU Embeddedoption iii Base BoostAll core MaxEPYC 7251 118 119 8 16 2 1 2 9 2 9 32 MB 120 W 4 CCD 8 1 Jun 2017 120 US 475 Yes7261 118 121 2 5 64 MB 155 170 W Jun 2018 122 US 570 Yes7281 118 119 16 32 2 1 2 7 2 7 32 MB 8 2 Jun 2017 120 US 650 Yes7301 118 119 2 2 64 MB US 800 Yes7351P 118 119 2 4 2 9 2 9 US 750 735P7351 118 119 US 1100 Yes7371 118 123 3 1 3 6 3 8 200 W Nov 2018 124 US 1550 Yes7401P 118 119 24 48 2 0 2 8 3 0 155 170 W 8 3 Jun 2017 120 US 1075 740P7401 118 119 US 1850 Yes7451 118 119 2 3 2 9 3 2 180 W US 2400 Yes7501 118 119 32 64 2 0 2 6 3 0 155 170 W 8 4 US 3400 Yes7551P 118 119 2 55 180 W US 2100 755P7551 118 119 US 3400 Yes7571 125 126 2 2 3 0 200 W Nov 2018 OEM AWS Un known7601 118 119 2 7 3 2 180 W Jun 2017 120 US 4200 Yesvte Models with P suffixes are uniprocessors only available as single socket configuration Core Complexes CCX cores per CCX EPYC Embedded 7001 series models have identical specifications as EPYC 7001 series Embedded server processors edit In February 2018 AMD also announced the EPYC 3000 series of embedded Zen CPUs 127 Common features of EPYC Embedded 3000 series CPUs Socket SP4 31xx and 32xx models use SP4r2 package All the CPUs support ECC DDR4 2666 in dual channel mode 3201 supports only DDR4 2133 while 33xx and 34xx models support quad channel mode L1 cache 96 KB 32 KB data 64 KB instruction per core L2 cache 512 KB per core All the CPUs support 32 PCIe 3 0 lanes per CCD max 64 lanes Fabrication process GlobalFoundries 14 nm Brand Model Cores threads Clock rate GHz L3 cache total TDP Chiplets Coreconfig i ReleasedateBase BoostAll core MaxEPYCEmbedded 3101 128 4 4 2 1 2 9 2 9 8 MB 35 W 1 x CCD 1 4 Feb 20183151 128 4 8 2 7 16 MB 45 W 2 23201 128 8 8 1 5 3 1 3 1 30 W 2 43251 128 8 16 2 5 55 W3255 129 25 55 W Dec 20183301 128 12 12 2 0 2 15 3 0 32 MB 65 W 2 x CCD 4 3 Feb 20183351 128 12 24 1 9 2 75 60 80 W3401 128 16 16 1 85 2 25 85 W 4 43451 128 16 32 2 15 2 45 80 100 Wvte Core Complexes CCX cores per CCXSee also edit nbsp Wikimedia Commons has media related to Zen microarchitecture AMD K9 AMD K10 Jim Keller engineer Ryzen Steamroller microarchitecture Zen Zen 2References edit AMD Ryzen 7 Desktop Processors Featuring Record Breaking Overclocking Performance Available Worldwide Today Press release Sunnyvale California Advanced Micro Devices Inc 2017 03 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2023 AMD EPYC Embedded 3255 PE3255BGR88AF CPU World March 26 2023 External links editRyzen Processors AMD Retrieved from https en wikipedia org w index php title Zen first generation amp oldid 1177516806, wikipedia, wiki, book, books, library,

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