14 nm process

The 12 nm, 14 nm, and 16 nm fabrication nodes are discussed here.

The 14 nm process refers to the MOSFET technology node that is the successor to the 22 nm (or 20 nm) node. The 14 nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22 nm was expected to be 16 nm. All 14 nm nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.

Samsung Electronics taped out a 14 nm chip in 2014, before manufacturing 10 nm class NAND flash chips in 2013.^{[clarification needed]} The same year, SK Hynix began mass-production of 16 nm NAND flash, and TSMC began 16 nm FinFET production. The following year, Intel began shipping 14 nm scale devices to consumers.

History

Background

14 nm resolution is difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick,^[1] but can also go up to about 100 nm.^[2] The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the 16/14 nm node circa 2010.^[3] Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.^[4] Mentor Graphics reported taping out 16 nm test chips in 2010.^[5] On January 17, 2011, IBM announced that they were teaming up with ARM to develop 14 nm chip processing technology.^[6]

On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the 14 nm manufacturing processes and leading-edge 300 mm wafers.^[7][8] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel has since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.^[9] On May 17, 2011, Intel announced a roadmap for 2014 that included 14 nm transistors for their Xeon, Core, and Atom product lines.^[10]

Technology demos

In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17 nm process. They later developed a 15 nm FinFET process in 2001.^[11] In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10 nm gate length.^[11][12]

In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process.^[13] It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.^[14] In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.^[15]

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a 16 nm SRAM chip.^[16]

In September 2011, Hynix announced the development of 15 nm NAND cells.^[17]

In December 2012, Samsung Electronics taped out a 14 nm chip.^[18]

In September 2013, Intel demonstrated an Ultrabook laptop that used a 14 nm Broadwell CPU, and Intel CEO Brian Krzanich said, "[CPU] will be shipping by the end of this year."^[19] However, shipment was delayed further until Q4 2014.^[20]

In August 2014, Intel announced details of the 14 nm microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's 14 nm manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.^[21]

In 2018 a shortage of 14 nm fab capacity was announced by Intel.^[22]

Shipping devices

In 2013, SK Hynix began mass-production of 16 nm NAND flash,^[23] TSMC began 16 nm FinFET production,^[24] and Samsung began 10 nm class NAND flash production.^[25]

On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.^[26]

In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature 14 nm Exynos systems on chip (SoCs).^[27]

On March 9, 2015, Apple Inc. released the "Early 2015" MacBook and MacBook Pro, which utilized 14 nm Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.^[28][29]

On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which are equipped with "desktop-class" A9 chips^[30] that are fabricated in both 14 nm by Samsung and 16 nm by TSMC (Taiwan Semiconductor Manufacturing Company).

In May 2016, Nvidia released its GeForce 10 series GPUs based on the Pascal architecture, which incorporates TSMC's 16 nm FinFET technology and Samsung's 14 nm FinFET technology.^[31][32]

In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporates 14 nm FinFET technology from Samsung. The technology was licensed to GlobalFoundries for dual sourcing.^[33]

On August 2, 2016, Microsoft released the Xbox One S, which utilized 16 nm by TSMC.

On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating 14 nm FinFET technology from Samsung which was licensed to GlobalFoundries for GlobalFoundries to build.^[34]

The NEC SX-Aurora TSUBASA processor, introduced in October 2017,^[35] uses a 16 nm FinFET process from TSMC and is designed for use with NEC SX supercomputers.^[36]

On July 22, 2018, GlobalFoundries announced their 12 nm Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.^[37]

In September 2018 Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's 12 nm process and have a transistor density of 24.67 million transistors per square millimeter.^[38]

14 nm process nodes

	ITRS Logic Device Ground Rules (2015)	Samsung^[a]	TSMC^[39]				Intel	GlobalFoundries^[b]		SMIC
Process name	16/14 nm	14/11 nm	16FF (16 nm)	16FF+ (16 nm)	16FFC (16 nm)	12FFC (12 nm)	14 nm	14LPP^[40] (14 nm)	12LP^[41]^[42] (12 nm)	14 nm
Transistor density (MTr/mm^2)	?	32.94^[37] (14 nm) 54.38^[37] (11 nm)	28.88^[43]			33.8^[44]	37.5^[45]^[c]	30.59^[37]	36.71^[37]	30^[47]
Transistor gate pitch (nm)	70	78 – 14LPE (HD) 78 – 14LPP (HD) 84 – 14LPP (UHP) 84 – 14LPP (HP) 78 – 11LPP (UHD)	88				70 (14 nm) 70 (14 nm +) 84 (14 nm ++)	84		?
Interconnect pitch (nm)	56	67	70				52	?		?
Transistor fin pitch (nm)	42	49	45				42	48		?
Transistor fin width (nm)	8	8	?				8	?		?
Transistor fin height (nm)	42	~38	37				42	?		?
Production year	2015	2013	2013	2015	2016	2017	2014	2016	2018	2019

1. Second-sourced to GlobalFoundries.
2. Based on Samsung's 14 nm process.
3. Intel uses this formula:^[46] ${\displaystyle {\rm {0.6\times {\frac {NAND2\ Tr\ Count}{NAND2\ Cell\ Area}}+0.4\times {\frac {Scan\ Flip\ Flop\ Tr\ Count}{Scan\ Flip\ Flop\ Cell\ Area}}=}}}$  # ${\displaystyle {\rm {Transistors/mm^{2}}}}$ 

Lower numbers are better, except for transistor density, in which case is the opposite.^[48] Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).^{[49][50][51][52][53]}

^[54]

References

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Preceded by 22 nm

MOSFET manufacturing processes

Succeeded by 10 nm