A common chiplet interconnect specification enables construction of large System-on-Chip (SoC) packages that exceed maximum reticle size. It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies. Each chiplet can use a different silicon manufacturing process, suitable for a specific device type, or computing performance and power draw requirements.[3][4]
Specificationsedit
The UCIe 1.0 specification was released on March 2, 2022.[5] It defines physical layer, protocol stack and software model, as well as procedures for compliance testing. The physical layer supports up to 32 GT/s with 16 to 64 lanes and uses a 256 byte Flow Control Unit (FLIT) for data, similar to PCIe 6.0; the protocol layer is based on Compute Express Link with CXL.io (PCIe), CXL.mem and CXL.cache protocols.
Various on-die interconnect technologies are defined, like organic substrate for a 'standard' 2D package, or embedded silicon bridge (EMIB), silicon interposer, and fanout embedded bridge for 'advanced' 2.5D/3D packages.[3] Physical specifications are based on Intel's Advanced Interface Bus (AIB).[4][6][7]
Shorter signal paths allow the links to have 20× better I/O performance and power consumption (~0.5 pJ per bit) comparing to typical PCIe SerDes, with bandwidth density up to 1.35 TB/s per mm2 for a common bump pitch of 45 μm, and 3.24× higher density with a bump pitch of 25 μm.[3]
Future versions may include additional protocols, wider data links, and higher density connections.[3]
The UCIe 1.1 specification was released on August 8, 2023.[8]
^"UCIe Announces Incorporation and New Board Members at FMS 2022". uciexpress.org. Retrieved 2022-12-14.
^ abcd"Universal Chiplet Interconnect Express (UCIe): Building an open chiplet ecosystem" (PDF). uciexpress.org. Retrieved 3 September 2023.
^ ab"Universal Chiplet Interconnect Express (UCIe) Announced: Setting Standards for the Chiplet Ecosystem".
^"Leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers join forces to standardize chiplet ecosystem" (PDF). uciexpress.org. Retrieved 3 September 2023.
^"UCIe (Universal Chiplet Interconnect Express) Consortium Releases its 1.1 Specification" (PDF). uciexpress.org. Retrieved 13 September 2023.
External linksedit
Official website
January 01, 1970
ucie, universal, chiplet, interconnect, express, open, specification, interconnect, serial, between, chiplets, developed, group, google, cloud, intel, meta, microsoft, qualcomm, samsung, tsmc, august, 2022, alibaba, group, nvidia, joined, board, members, conte. Universal Chiplet Interconnect Express UCIe is an open specification for a die to die interconnect and serial bus between chiplets It is co developed by AMD Arm ASE Group Google Cloud Intel Meta Microsoft Qualcomm Samsung and TSMC 1 In August 2022 Alibaba Group and Nvidia joined as board members 2 Contents 1 Overview 2 Specifications 3 References 4 External linksOverview editA common chiplet interconnect specification enables construction of large System on Chip SoC packages that exceed maximum reticle size It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies Each chiplet can use a different silicon manufacturing process suitable for a specific device type or computing performance and power draw requirements 3 4 Specifications editThe UCIe 1 0 specification was released on March 2 2022 5 It defines physical layer protocol stack and software model as well as procedures for compliance testing The physical layer supports up to 32 GT s with 16 to 64 lanes and uses a 256 byte Flow Control Unit FLIT for data similar to PCIe 6 0 the protocol layer is based on Compute Express Link with CXL io PCIe CXL mem and CXL cache protocols Various on die interconnect technologies are defined like organic substrate for a standard 2D package or embedded silicon bridge EMIB silicon interposer and fanout embedded bridge for advanced 2 5D 3D packages 3 Physical specifications are based on Intel s Advanced Interface Bus AIB 4 6 7 Shorter signal paths allow the links to have 20 better I O performance and power consumption 0 5 pJ per bit comparing to typical PCIe SerDes with bandwidth density up to 1 35 TB s per mm2 for a common bump pitch of 45 mm and 3 24 higher density with a bump pitch of 25 mm 3 Future versions may include additional protocols wider data links and higher density connections 3 The UCIe 1 1 specification was released on August 8 2023 8 References edit About UCIe uciexpress org Retrieved 2022 03 31 UCIe Announces Incorporation and New Board Members at FMS 2022 uciexpress org Retrieved 2022 12 14 a b c d Universal Chiplet Interconnect Express UCIe Building an open chiplet ecosystem PDF uciexpress org Retrieved 3 September 2023 a b Universal Chiplet Interconnect Express UCIe Announced Setting Standards for the Chiplet Ecosystem Leaders in semiconductors packaging IP suppliers foundries and cloud service providers join forces to standardize chiplet ecosystem PDF uciexpress org Retrieved 3 September 2023 Intel Joins CHIPS Alliance Contributes Advanced Interface Bus AIB specification GitHub 20 April 2022 UCIe Universal Chiplet Interconnect Express Consortium Releases its 1 1 Specification PDF uciexpress org Retrieved 13 September 2023 External links editOfficial website Retrieved from https en wikipedia org w index php title UCIe amp oldid 1220985317, wikipedia, wiki, book, books, library,
