OpenTitan is the first open source silicon Root of Trust (RoT) project.[2] It is designed to be integrated into data center servers, storage devices, peripherals and other hardware.[3] OpenTitan is under the stewardship of lowRISC and collaboratively developed by Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital.[4] The OpenTitan source code is available on GitHub, released under the permissiveApache 2 license.
Ibex CPU coreedit
Ibex is an embedded open source 32-bit in-order RISC-VCPU core, which has been taped out multiple times.[5] Ibex is used in the OpenTitan chip. Development on Ibex started in 2015 under the name "Zero-riscy" and "Micro-riscy" at the ETH Zurich and University of Bologna, where it was part of the PULP platform. In December 2018 lowRISC took over the development.[6] Luca Benini of the ETH Zurich sits on lowRISC' board.
Prototype 64-bit SoC designedit
The lowRISC prototype 64-bit SoC design is an open source Linux-capable 64-bit RISC-VSoC design. A first version preview release of the source code was made available in April 2015.[7] Since then features were added, such as support for tagged memory and "minion cores", small CPU cores which are dedicated to I/O tasks.[8] The latest version 0.6 was released in November 2018,[9] and is available to download and try out on an FPGA.
Other projectsedit
lowRISC initiated and led the upstreaming of the RISC-VLLVM backend, where Alex Bradbury is code owner.[10]
Additionally, Mark Hayter of Google sits on the board as an observer.[1]
Historyedit
lowRISC was spun out of the University of CambridgeComputer Lab in 2014 by Alex Bradbury, Robert Mullins, and Gavin Ferris[1] with the goal of creating a fully open source SoC and low-cost development board.[11][12]
Since 2018 lowRISC has been focusing on collaborative engineering with partner organizations. In 2019 the OpenTitan project, stewarded by lowRISC, was announced.[14]
Referencesedit
^ abc"About lowRISC". lowrisc.org. Retrieved 24 March 2021.
^Anderson, Tim (5 Nov 2019). "Cambridge boffins and Google unveil open-source OpenTitan chip – because you never know who you can trust". The Register. Retrieved 24 March 2021.
^"Open source silicon Root of Trust". opentitan.org.
^"OpenTitan partners". opentitan.org. Retrieved 24 March 2021.
^"Ibex: An embedded 32 bit RISC-V CPU core". Retrieved 24 March 2021.
^"Ibex Reference Guide: History". Retrieved 24 March 2021.
^"lowRISC tagged memory preview release". lowrisc.org. April 13, 2015. Retrieved 24 March 2021.
^"Overview of the minion infrastructure". lowrisc.org. Retrieved 24 March 2021.
^"lowRISC 0-6 milestone release". lowrisc.org. 2018-11-12. Retrieved 24 March 2021.
^Bradbury, Alex. "The RISC-V LLVM backend in Clang/LLVM 9.0". lowrisc.org. Retrieved 24 March 2021.
^"Free Core, Some Assembly Required". EETimes. 2016-01-07. Retrieved 24 March 2021.
^"Founding Members". riscv.org. Retrieved 24 March 2021.
^Bradbury, Alex (2019-11-05). "Announcing OpenTitan, the First Transparent Silicon Root of Trust".
External linksedit
Official website
February 16, 2024
lowrisc, profit, company, headquartered, cambridge, uses, collaborative, engineering, develop, maintain, open, source, silicon, designs, tools, active, risc, related, open, source, hardware, software, development, stewards, opentitan, project, company, typepri. lowRISC C I C is a not for profit company headquartered in Cambridge UK It uses collaborative engineering to develop and maintain open source silicon designs and tools 1 lowRISC is active in RISC V related open source hardware and software development and stewards the OpenTitan project lowRISC C I C Company typePrivateFoundedOctober 20 2014 9 years ago 2014 10 20 in Cambridge UKFoundersGavin Ferris Alex Bradbury Robert MullinsHeadquartersCambridge United KingdomProductsIbex OpenTitanWebsitelowrisc wbr org Contents 1 Projects 1 1 OpenTitan 1 2 Ibex CPU core 1 3 Prototype 64 bit SoC design 1 4 Other projects 2 Governance 2 1 Board of directors 3 History 4 References 5 External linksProjects editOpenTitan edit OpenTitan is the first open source silicon Root of Trust RoT project 2 It is designed to be integrated into data center servers storage devices peripherals and other hardware 3 OpenTitan is under the stewardship of lowRISC and collaboratively developed by Google ETH Zurich Nuvoton G D Mobile Security Seagate and Western Digital 4 The OpenTitan source code is available on GitHub released under the permissive Apache 2 license Ibex CPU core edit Ibex is an embedded open source 32 bit in order RISC V CPU core which has been taped out multiple times 5 Ibex is used in the OpenTitan chip Development on Ibex started in 2015 under the name Zero riscy and Micro riscy at the ETH Zurich and University of Bologna where it was part of the PULP platform In December 2018 lowRISC took over the development 6 Luca Benini of the ETH Zurich sits on lowRISC board Prototype 64 bit SoC design edit The lowRISC prototype 64 bit SoC design is an open source Linux capable 64 bit RISC V SoC design A first version preview release of the source code was made available in April 2015 7 Since then features were added such as support for tagged memory and minion cores small CPU cores which are dedicated to I O tasks 8 The latest version 0 6 was released in November 2018 9 and is available to download and try out on an FPGA Other projects edit lowRISC initiated and led the upstreaming of the RISC V LLVM backend where Alex Bradbury is code owner 10 Governance editBoard of directors edit Andy Hopper Independent Chair Will Drewry Google Gavin Ferris CEO lowRISC Robert Mullins University of Cambridge Claudia Eckert TU Munich Fraunhofer AISEC Cyrus Stoller Google Additionally Mark Hayter of Google sits on the board as an observer 1 History editlowRISC was spun out of the University of Cambridge Computer Lab in 2014 by Alex Bradbury Robert Mullins and Gavin Ferris 1 with the goal of creating a fully open source SoC and low cost development board 11 12 In 2015 lowRISC became one of the founding members of the RISC V Foundation today RISC V International 13 Since 2018 lowRISC has been focusing on collaborative engineering with partner organizations In 2019 the OpenTitan project stewarded by lowRISC was announced 14 References edit a b c About lowRISC lowrisc org Retrieved 24 March 2021 Anderson Tim 5 Nov 2019 Cambridge boffins and Google unveil open source OpenTitan chip because you never know who you can trust The Register Retrieved 24 March 2021 Open source silicon Root of Trust opentitan org OpenTitan partners opentitan org Retrieved 24 March 2021 Ibex An embedded 32 bit RISC V CPU core Retrieved 24 March 2021 Ibex Reference Guide History Retrieved 24 March 2021 lowRISC tagged memory preview release lowrisc org April 13 2015 Retrieved 24 March 2021 Overview of the minion infrastructure lowrisc org Retrieved 24 March 2021 lowRISC 0 6 milestone release lowrisc org 2018 11 12 Retrieved 24 March 2021 Bradbury Alex The RISC V LLVM backend in Clang LLVM 9 0 lowrisc org Retrieved 24 March 2021 Free Core Some Assembly Required EETimes 2016 01 07 Retrieved 24 March 2021 LowRISC SoC 1st RISC V Workshop YouTube Founding Members riscv org Retrieved 24 March 2021 Bradbury Alex 2019 11 05 Announcing OpenTitan the First Transparent Silicon Root of Trust External links editOfficial website nbsp Retrieved from https en wikipedia org w index php title LowRISC amp oldid 1206080571, wikipedia, wiki, book, books, library,
