The P6 microarchitecture is the sixth-generation Intelx86microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686.[2] It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.
P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).
The P6 core was the sixth generation Intel microprocessor in the x86 line. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).
P6 processors dynamically translate IA-32 instructions into sequences of buffered RISC-like micro-operations, then analyze and reorder the micro-operations to detect parallelizable operations that may be issued to more than one execution unit at once.[3] The Pentium Pro was the first x86 microprocessor designed by Intel to use this technique, though the NexGen Nx586, introduced in 1994, did so earlier.
Other features first implemented in the x86 space in the P6 core include:
Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro and early model of the Pentium III (Coppermine), and eventually morphed into less than 10-stage pipeline of the Pentium M for embedded and mobile market due to energy inefficiency and higher voltage issues that encountered in the predecessor, and then again lengthening the 10- to 12-stage pipeline back to the Core 2 due to facing difficulty increasing clock speed while improving fabrication process can somehow negate some negative impact of higher power consumption on the deeper pipeline design.
A front-side bus using a variant of Gunning transceiver logic to enable four discrete processors to share system resources.[4]
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. NetBurst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors without significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life. Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the Pentium M.
Quad-pumped front-side bus. With the initial Banias core, Intel adopted the 400 MT/s FSB first used in Pentium 4. The Dothan core moved to the 533 MT/s FSB, following Pentium 4's evolution.
Larger L1/L2 cache. L1 cache increased from predecessor's 32 KB to current 64 KB in all models. Initially 1 MB L2 cache in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states.
A 10- or 12-stage Enhanced instruction pipeline that allows for higher clock speeds without lengthening the pipeline stage, reduced from 14 stage on Pentium Pro/II/III.
Dedicated register stack management.
Addition of global history, indirect prediction, and loop prediction to branch prediction table. Removal of local prediction.
Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can result in fewer micro-operations and thus require fewer processor cycles to complete.
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.[6] The first Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels.[7]
The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the Pentium M's shortcomings by adding:
SSE3 Support
Single- and dual-core technology with 2 MB of shared L2 cache (restructuring processor organization)
Increased FSB speed, with the FSB running at 533 MT/s or 667 MT/s.
A 12-stage instruction pipeline.
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
On July 27, 2006, the Core microarchitecture, a derivative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, Xeon, Pentium and Celeron brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB, with all later Intel processors based on Nehalem and later Intel microarchitectures featuring an integrated memory controller and a QPI or DMI bus for communication with the rest of the system. Improvements relative to the Intel Core processors were:
A 14-stage instruction pipeline that allows for higher clock speeds.
SSE4.1 support for all Core 2 models manufactured at a 45 nm lithography.
Support for the 64-bit x86-64 architecture, which was previously only offered by Prescott processors, the Pentium 4 last architectural installment.
Increased FSB speed, ranging from 533 MT/s to 1600 MT/s.
Increased L2 cache size, with the L2 cache size ranging from 1 MB to 12 MB (Core 2 Duo processors use a shared L2 cache while Core 2 Quad processors having half of the total cache is shared by each core pair).
Dynamic Front Side Bus Throttling (some mobile models), where the speed of the FSB is reduced in half, which by extension reduces the processor's speed in half. Thus the processor goes to a low power consumption mode called Super Low Frequency Mode that helps extend battery life.
Dynamic Acceleration Technology for some mobile Core 2 Duo processors, and Dual Dynamic Acceleration Technology for mobile Core 2 Quad processors. Dynamic Acceleration Technology allows the CPU to overclock one processor core while turning off the one. In Dual Dynamic Acceleration Technology two cores are deactivated and two cores are overclocked. This feature is triggered when an application only uses a single core for Core 2 Duo or up to two cores for Core 2 Quad. The overclocking is performed by increasing the clock multiplier by 1.
While all these chips are technically derivatives of the Pentium Pro, the architecture has gone through several radical changes since its inception.[8]
microarchitecture, this, article, needs, additional, citations, verification, please, help, improve, this, article, adding, citations, reliable, sources, unsourced, material, challenged, removed, find, sources, microarchitecture, news, newspapers, books, schol. This article needs additional citations for verification Please help improve this article by adding citations to reliable sources Unsourced material may be challenged and removed Find sources P6 microarchitecture news newspapers books scholar JSTOR June 2013 Learn how and when to remove this template message The P6 microarchitecture is the sixth generation Intel x86 microarchitecture implemented by the Pentium Pro microprocessor that was introduced in November 1995 It is frequently referred to as i686 2 It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000 but was revived for the Pentium M line of microprocessors The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6 P6Die shot of Deschutes coreGeneral informationLaunchedNovember 1 1995 27 years ago November 1 1995 PerformanceMax CPU clock rate150 1 MHz to 1 40 GHzFSB speeds66 MHz to 133 MHzCacheL1 cachePentium Pro 16 KB 8 KB I cache 8 KB D cache Pentium II III 32 KB 16 KB I cache 16 KB D cache L2 cache128 KB to 512 KB256 KB to 2048 KB Xeon Architecture and classificationMicroarchitectureP6Instruction setx86ExtensionsMMX Pentium II III SSE Pentium III Physical specificationsTransistors5 5M 500 nm7 5M 350 nm7 5M 250 nm B0 B1 9 5M 250 nm B0 C0 19M 250 nm B0 28M 180 nm A1 A2 B0 C0 D0 44M 130 nm A1 B1 C1 D0 Cores1Socket s Socket 8Slot 1Socket 370Socket 479Products models variantsModel s Celeron SeriesPentium II SeriesPentium III SeriesPentium Pro SeriesPentium II Xeon SeriesPentium III Xeon SeriesVariant s Pentium MEnhanced Pentium MHistoryPredecessorP5SuccessorNetBurst Pentium MSupport statusUnsupportedP6 was used within Intel s mainstream offerings from the Pentium Pro to Pentium III and was widely known for low power consumption excellent integer performance and relatively high instructions per cycle IPC Contents 1 Features 1 1 P6 based chips 2 P6 Variant Pentium M 2 1 Banias Dothan variant 3 P6 Variant Enhanced Pentium M 3 1 Yonah variant 4 Successor 5 See also 6 ReferencesFeatures EditThe P6 core was the sixth generation Intel microprocessor in the x86 line The first implementation of the P6 core was the Pentium Pro CPU in 1995 the immediate successor to the original Pentium design P5 P6 processors dynamically translate IA 32 instructions into sequences of buffered RISC like micro operations then analyze and reorder the micro operations to detect parallelizable operations that may be issued to more than one execution unit at once 3 The Pentium Pro was the first x86 microprocessor designed by Intel to use this technique though the NexGen Nx586 introduced in 1994 did so earlier Other features first implemented in the x86 space in the P6 core include Speculative execution and out of order completion called dynamic execution by Intel which required new retire units in the execution core This lessened pipeline stalls and in part enabled greater speed scaling of the Pentium Pro and successive generations of CPUs Superpipelining which increased from Pentium s 5 stage pipeline to 14 of the Pentium Pro and early model of the Pentium III Coppermine and eventually morphed into less than 10 stage pipeline of the Pentium M for embedded and mobile market due to energy inefficiency and higher voltage issues that encountered in the predecessor and then again lengthening the 10 to 12 stage pipeline back to the Core 2 due to facing difficulty increasing clock speed while improving fabrication process can somehow negate some negative impact of higher power consumption on the deeper pipeline design A front side bus using a variant of Gunning transceiver logic to enable four discrete processors to share system resources 4 Physical Address Extension PAE and a wider 36 bit address bus to support 64 GB of physical memory 5 Register renaming which enabled more efficient execution of multiple instructions in the pipeline CMOV instructions which are heavily used in compiler optimization Other new instructions FCMOV FCOMI FCOMIP FUCOMI FUCOMIP RDPMC UD2 New instructions in Pentium II Deschutes core MMX FXSAVE FXRSTOR New instructions in Pentium III Streaming SIMD Extensions P6 based chips Edit Celeron Covington Mendocino Coppermine Tualatin variants Pentium Pro Pentium II Overdrive a Pentium II chip in the 387 pin Socket 8 Pentium II Pentium II Xeon Pentium III Pentium III XeonP6 Variant Pentium M EditMain article Pentium M P6 Pentium M General informationLaunchedMarch 12 2003PerformanceMax CPU clock rate600 MHz to 2 26 GHzFSB speeds400 MT s to 533 MT sCacheL1 cache64KB 32 KB I Cache 32 KB D cache L2 cache512 KB to 2048 KBArchitecture and classificationMicroarchitectureP6Instruction setx86ExtensionsMMX SSE SSE2Physical specificationsTransistors77M 130 nm B1 B2 144M 90 nm B0 C0 151M 65 nm C0 D0 Cores1Socket s Socket MProducts models variantsModel s A100 SeriesEP80579 SeriesCeleron M SeriesPentium M SeriesHistoryPredecessorNetBurstSuccessorEnhanced Pentium MSupport statusUnsupportedUpon release of the Pentium 4 M and Mobile Pentium 4 it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing NetBurst based processors were simply not as efficient per clock or per watt compared to their P6 predecessors Mobile Pentium 4 processors ran much hotter than Pentium III M processors without significant performance advantages Its inefficiency affected not only the cooling system complexity but also the all important battery life Intel went back to the drawing board for a design that would be optimally suited for this market segment The result was a modernized P6 design called the Pentium M Design Overview 6 Quad pumped front side bus With the initial Banias core Intel adopted the 400 MT s FSB first used in Pentium 4 The Dothan core moved to the 533 MT s FSB following Pentium 4 s evolution Larger L1 L2 cache L1 cache increased from predecessor s 32 KB to current 64 KB in all models Initially 1 MB L2 cache in the Banias core then 2 MB in the Dothan core Dynamic cache activation by quadrant selector from sleep states SSE2 Streaming SIMD Extensions 2 support A 10 or 12 stage Enhanced instruction pipeline that allows for higher clock speeds without lengthening the pipeline stage reduced from 14 stage on Pentium Pro II III Dedicated register stack management Addition of global history indirect prediction and loop prediction to branch prediction table Removal of local prediction Micro ops Fusion of certain sub instructions mediated by decoding units x86 commands can result in fewer micro operations and thus require fewer processor cycles to complete The Pentium M was the most power efficient x86 processor for notebooks for several years consuming a maximum of 27 watts at maximum load and 4 5 watts while idle The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher the fastest clocked Mobile Pentium 4 compared to the fastest clocked Pentium M and equipped with much more memory and bus bandwidth 6 The first Pentium M family processors Banias internally support PAE but do not show the PAE support flag in their CPUID information this causes some operating systems primarily Linux distributions to refuse to boot on such processors since PAE support is required in their kernels 7 Banias Dothan variant Edit Celeron M Banias Shelton Dothan variants Pentium M A100 A110 EP80579 CE 3100P6 Variant Enhanced Pentium M EditMain article Yonah microprocessor P6 Enhanced Pentium MGeneral informationLaunched2006PerformanceMax CPU clock rate1 06 GHz to 2 33 GHzFSB speeds533 MT s to 667 MT sCacheL1 cache64 KBL2 cache1 MB to 2 MB2 MB Xeon Architecture and classificationMicroarchitectureP6Instruction setx86ExtensionsMMX SSE SSE2 SSE3Physical specificationsTransistors151M 65 nm C0 D0 Cores1 2Socket s Socket MProducts models variantsModel s Celeron M SeriesPentium Dual Core SeriesCore Solo SeriesCore Duo SeriesXeon LV SeriesHistoryPredecessorPentium MSuccessorIntel CoreSupport statusUnsupportedThe Yonah CPU was launched in January 2006 under the Core brand Single and dual core mobile version were sold under the Core Solo Core Duo and Pentium Dual Core brands and a server version was released as Xeon LV These processors provided partial solutions to some of the Pentium M s shortcomings by adding SSE3 Support Single and dual core technology with 2 MB of shared L2 cache restructuring processor organization Increased FSB speed with the FSB running at 533 MT s or 667 MT s A 12 stage instruction pipeline This resulted in the interim microarchitecture for low voltage only CPUs part way between P6 and the following Core microarchitecture Yonah variant Edit Celeron M 400 series Core Solo Duo Pentium Dual Core T2060 T2080 T2130 Xeon LV ULV Sossaman Successor EditIt has been suggested that parts of this page be moved into Intel Core microarchitecture Relevant discussion may be found on the talk page October 2021 On July 27 2006 the Core microarchitecture a derivative of P6 was launched in form of the Core 2 processor Subsequently more processors were released with the Core microarchitecture under Core 2 Xeon Pentium and Celeron brand names The Core microarchitecture is Intel s final mainstream processor line to use FSB with all later Intel processors based on Nehalem and later Intel microarchitectures featuring an integrated memory controller and a QPI or DMI bus for communication with the rest of the system Improvements relative to the Intel Core processors were A 14 stage instruction pipeline that allows for higher clock speeds SSE4 1 support for all Core 2 models manufactured at a 45 nm lithography Support for the 64 bit x86 64 architecture which was previously only offered by Prescott processors the Pentium 4 last architectural installment Increased FSB speed ranging from 533 MT s to 1600 MT s Increased L2 cache size with the L2 cache size ranging from 1 MB to 12 MB Core 2 Duo processors use a shared L2 cache while Core 2 Quad processors having half of the total cache is shared by each core pair Dynamic Front Side Bus Throttling some mobile models where the speed of the FSB is reduced in half which by extension reduces the processor s speed in half Thus the processor goes to a low power consumption mode called Super Low Frequency Mode that helps extend battery life Dynamic Acceleration Technology for some mobile Core 2 Duo processors and Dual Dynamic Acceleration Technology for mobile Core 2 Quad processors Dynamic Acceleration Technology allows the CPU to overclock one processor core while turning off the one In Dual Dynamic Acceleration Technology two cores are deactivated and two cores are overclocked This feature is triggered when an application only uses a single core for Core 2 Duo or up to two cores for Core 2 Quad The overclocking is performed by increasing the clock multiplier by 1 While all these chips are technically derivatives of the Pentium Pro the architecture has gone through several radical changes since its inception 8 See also EditList of Intel CPU microarchitecturesReferences Edit Pentium Pro Processor at 150 MHz 166 MHz 180 MHz and 200 MHz PDF Intel Corporation November 1995 p 1 Archived from the original PDF on April 2 2016 Hutchings Ben September 28 2015 Defaulting to i686 for the Debian i386 architecture debian devel Mailing list Gwennap Linley February 16 1995 Intel s P6 Uses Decoupled Scalar Design PDF Microprocessor Report 9 2 Pentium and Pentium Pro Processors and Related Products Intel Corporation December 1995 pp 1 10 ISBN 1 55512 251 5 Brey Barry 2009 The Intel Microprocessors PDF 8th ed Upper Saddle River N J Pearson Prentice Hall p 754 ISBN 978 0 13 502645 8 a b Lal Shimpi Anand Intel s 90nm Pentium M 755 Dothan Investigated AnandTech July 21 2004 PAE Community Help Wiki help ubuntu com Pat Gelsinger talk at Stanford Jun 7th 2006 Archived from the original on June 3 2011 Retrieved from https en wikipedia org w index php title P6 microarchitecture amp oldid 1147079910, wikipedia, wiki, book, books, library,
