Physical layer

"PHY" redirects here. For other uses, see PHY (disambiguation).

In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer: the layer most closely associated with the physical connection between devices. The physical layer provides an electrical, mechanical, and procedural interface to the transmission medium. The shapes and properties of the electrical connectors, the frequencies to transmit on, the line code to use and similar low-level parameters, are specified by the physical layer.

At the electrical layer, the physical layer is commonly implemented by dedicated PHY chip or, in electronic design automation (EDA), by a design block. In mobile computing, the MIPI Alliance *-PHY family of interconnect protocols are widely used.

Historically, the OSI model is closely associated with internetworking, such as the Internet protocol suite and Ethernet, which were developed in the same era, along similar lines, though with somewhat different abstractions. Beyond internetworking, the OSI abstraction can be brought to bear on all forms of device interconnection in data communications and computational electronics.

Role

The physical layer defines the means of transmitting a stream of raw bits^[2] over a physical data link connecting network nodes. The bitstream may be grouped into code words or symbols and converted to a physical signal that is transmitted over a transmission medium.

The physical layer consists of the electronic circuit transmission technologies of a network.^[3] It is a fundamental layer underlying the higher level functions in a network, and can be implemented through a great number of different hardware technologies with widely varying characteristics.^[4]

Within the semantics of the OSI model, the physical layer translates logical communications requests from the data link layer into hardware-specific operations to cause transmission or reception of electronic (or other) signals.^[5][6] The physical layer supports higher layers responsible for generation of logical data packets.

Physical signaling sublayer

In a network using Open Systems Interconnection (OSI) architecture, the physical signaling sublayer is the portion of the physical layer that^[7][8]

• interfaces with the data link layer's medium access control (MAC) sublayer,
• performs symbol encoding, transmission, reception and decoding and,
• performs galvanic isolation.

Relation to the Internet protocol suite

The Internet protocol suite, as defined in RFC 1122 and RFC 1123, is a high-level networking description used for the Internet and similar networks. It does not define a layer that deals exclusively with hardware-level specifications and interfaces, as this model does not concern itself directly with physical interfaces.^[9][10]

Services

The major functions and services performed by the physical layer are: The physical layer performs bit-by-bit or symbol-by-symbol data delivery over a physical transmission medium.^[11] It provides a standardized interface to the transmission medium, including^[12][13] a mechanical specification of electrical connectors and cables, for example maximum cable length, an electrical specification of transmission line signal level and impedance. The physical layer is responsible for electromagnetic compatibility including electromagnetic spectrum frequency allocation and specification of signal strength, analog bandwidth, etc. The transmission medium may be electrical or optical over optical fiber or a wireless communication link such as free-space optical communication or radio.

Line coding is used to convert data into a pattern of electrical fluctuations which may be modulated onto a carrier wave or infrared light. The flow of data is managed with bit synchronization in synchronous serial communication or start-stop signalling and flow control in asynchronous serial communication. Sharing of the transmission medium among multiple network participants can be handled by simple circuit switching or multiplexing. More complex medium access control protocols for sharing the transmission medium may use carrier sense and collision detection such as in Ethernet's Carrier-sense multiple access with collision detection (CSMA/CD).

To optimize reliability and efficiency, signal processing techniques such as equalization, training sequences and pulse shaping may be used. Error correction codes and techniques including forward error correction^[14] may be applied to further improve reliability.

Other topics associated with the physical layer include: bit rate; point-to-point, multipoint or point-to-multipoint line configuration; physical network topology, for example bus, ring, mesh or star network; serial or parallel communication; simplex, half duplex or full duplex transmission mode; and autonegotiation^[15]

PHY

 

RTL8201 Ethernet PHY chip

 

Texas Instruments DP83825 – 3 × 3 mm 3.3 V PHY chip

"PHY" redirects here. For other uses, see PHY (disambiguation).

A PHY, an abbreviation for physical layer, is an electronic circuit, usually implemented as an integrated circuit, required to implement physical layer functions of the OSI model in a network interface controller.

A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes both physical coding sublayer (PCS) and physical medium dependent (PMD) layer functionality.^[16]

-PHY may also be used as a suffix to form a short name referencing a specific physical layer protocol, for example M-PHY.

Modular transceivers for fiber-optic communication (like the SFP family) complement a PHY chip and form the PMD sublayer.

Ethernet physical transceiver

 

Micrel KS8721CL – 3.3 V single power supply 10/100BASE-TX/FX MII physical layer transceiver

The Ethernet PHY is a component that operates at the physical layer of the OSI network model. It implements the physical layer portion of the Ethernet. Its purpose is to provide analog signal physical access to the link. It is usually interfaced with a media-independent interface (MII) to a MAC chip in a microcontroller or another system that takes care of the higher layer functions.

More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling.^[17] The PHY usually does not handle MAC addressing, as that is the link layer's job. Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Common Ethernet interfaces include fiber or two to four copper pairs for data communication. However, there now exists a new interface, called Single Pair Ethernet (SPE), which is able to utilize a single pair of copper wires while still communicating at the intended speeds. Texas Instruments DP83TD510E^[18] is an example of a PHY which uses SPE.

Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers, Texas Instruments DP838xx family^[19] and offerings from Intel^[20] and ICS.^[21]

Other applications

• Wireless LAN or Wi-Fi: The PHY portion consists of the RF, mixed-signal and analog portions, that are often called transceivers, and the digital baseband portion that use digital signal processor (DSP) and communication algorithm processing, including channel codes. It is common that these PHY portions are integrated with the medium access control (MAC) layer in system-on-a-chip (SOC) implementations. Similar wireless applications include 3G/4G/LTE/5G, WiMAX and UWB.
• Universal Serial Bus (USB): A PHY chip is integrated into most USB controllers in hosts or embedded systems and provides the bridge between the digital and modulated parts of the interface.
• IrDA: The Infrared Data Association's (IrDA) specification includes an IrPHY specification for the physical layer of the data transport.
• Serial ATA (SATA): Serial ATA controllers use a PHY.

Technologies

The following technologies provide physical layer services:^[22]

• 1-Wire
• ARINC 818 Avionics Digital Video Bus
• Bluetooth physical layer
• CAN bus (controller area network) physical layer
• DSL
• EIA RS-232, EIA-422, EIA-423, RS-449, RS-485
• Etherloop
• Ethernet physical layer Including 10BASE-T, 10BASE2, 10BASE5, 100BASE-TX, 100BASE-FX, 1000BASE-T, 1000BASE-SX and other varieties
• G.hn/G.9960 physical layer
• GSM Um air interface physical layer
• UMTS air interface physical layer
• LTE air interface physical layer
• 5G air interface physical layer
• Communications satellite technologies physical layers
• IEEE 802.15.4 physical layers
• IEEE 1394 interface
• IRDA physical layer
• ISDN
• ITU Recommendations: see ITU-T
• I²C, I²S
• LoRa
• Low-voltage differential signaling
• Mobile Industry Processor Interface physical layer
• Modulated ultrasound
• Optical Transport Network (OTN)
• SMB
• SONET/SDH
• SPI
• T1 and other T-carrier links, and E1 and other E-carrier links
• Telephone network modems — ITU-T V.92
• TransferJet physical layer
• USB physical layer
• PCI Express physical layer
• 802.11 Wi-Fi physical layer
• Visible light communication co-ordinated under IEEE 802.15.7
• X10

See also

• Channel model
• Clock recovery
• Data transmission
• Intrinsic safety
• SerDes

References

1. "X.225 : Information technology – Open Systems Interconnection – Connection-oriented Session protocol: Protocol specification". from the original on 1 February 2021. Retrieved 10 March 2023.
2. Gorry Fairhurst (2001-01-01). . Archived from the original on 2009-06-18.
3. Iyengar, Shisharama (2010). Fundamentals of Sensor Network Programming. Wiley. p. 136. ISBN 978-1423902454.
4. "The Physical Layer | InterWorks". InterWorks. 2011-07-30. Retrieved 2018-08-14.
5. Shaw, Keith (2018-10-22). "The OSI model explained: How to understand (and remember) the 7 layer network model". Network World. Retrieved 2019-02-15.
6. "DATA COMMUNICATION & NETWORKING". ResearchGate. Retrieved 2019-02-15.
7.   This article incorporates public domain material from . General Services Administration. Archived from the original on 2022-01-22.
8. . Archived from the original on 2010-12-27. Retrieved 2011-07-29.
9. "rfc1122". datatracker.ietf.org. Retrieved 2021-07-28.
10. "rfc1123". datatracker.ietf.org. Retrieved 2021-07-28.
11. Shekhar, Amar (2016-04-07). "Physical Layer Of OSI Model: Working Functionalities and Protocols". Fossbytes. Retrieved 2019-02-15.
12. Bayliss, Colin R.; Bayliss, Colin; Hardy, Brian (2012-02-14). Transmission and Distribution Electrical Engineering. Elsevier. ISBN 9780080969121.
13. "CCNA Certification/Physical Layer - Wikibooks, open books for an open world". en.wikibooks.org. Retrieved 2019-02-15.
14. Bertsekas, Dimitri; Gallager, Robert (1992). Data Networks. Prentice Hall. p. 61. ISBN 0-13-200916-1.
15. Forouzan, Behrouz A.; Fegan, Sophia Chung (2007). Data Communications and Networking. Huga Media. ISBN 9780072967753.
16. Mauricio Arregoces; Maurizio Portolani (2003). Data Center Fundamentals. ISBN 9781587050237. Retrieved 2015-11-18.
17. "microcontroller - what is the difference between PHY and MAC chip - Electrical Engineering Stack Exchange". Electronics.stackexchange.com. 2013-07-11. Retrieved 2015-11-18.
18. "DP83TD510E Ultra Low Power 802.3cg 10Base-T1L 10M Single Pair Ethernet PHY" (PDF). Texas Instruments. Retrieved 12 October 2020.
19. "Ethernet PHYs". Texas Instruments. Retrieved 12 October 2020.
20. Intel PHY controllers brochure
21. osuosl.org - ICS1890 10Base-T/100Base-TX Integrated PHYceiver datasheet
22. "Physical Layer | Layer 1". The OSI-Model. Retrieved 2021-07-28.

External links

• Physical Layer (Layer 1)
• 10G Layer 1 Walkthrough