CoreConnect is a microprocessorbus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA bus architecture, allowing reuse of existing SoC-components.
IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as Cadence, Ericsson, Lucent, Nokia, Siemens and Synopsys.
The CoreConnect is an integral part of IBM's embedded offerings and is used extensively in their PowerPC 4x0 based designs. In the past, Xilinx was using CoreConnect as the infrastructure for all of their embedded processor designs.
Processor Local Bus (PLB)edit
General processor local bus
Synchronous, nonmultiplexed bus
Separate Read, Write data buses
Supports concurrent Read, Writes
Multimaster, programmable-priority, arbitrated bus
provides fully synchronous movement of GPR data between CPU and slave logic
functions as a synchronous, nonmultiplexed bus
has separate buses to read and to write data
consists of a single-master, multiple-slave bus
includes a 10-bit address bus
features 32-bit data buses
uses two-cycle minimum Read/Write cycles
utilizes distributed multiplexer architecture
supports 8-, 16-, and 32-bit devices
performs single-cycle data transfers
External linksedit
CoreConnect licensing, IBM.com
January 01, 1970
coreconnect, microprocessor, architecture, from, system, chip, designs, designed, ease, integration, reuse, processor, system, peripheral, cores, within, standard, custom, designs, standard, design, point, serves, foundation, devices, elements, this, architect. CoreConnect is a microprocessor bus architecture from IBM for system on a chip SoC designs It was designed to ease the integration and reuse of processor system and peripheral cores within standard and custom SoC designs As a standard SoC design point it serves as the foundation of IBM or non IBM devices Elements of this architecture include the processor local bus PLB the on chip peripheral bus OPB a bus bridge and a device control register DCR bus High performance peripherals connect to the high bandwidth low latency PLB Slower peripheral cores connect to the OPB which reduces traffic on the PLB CoreConnect has bridging capabilities to the competing AMBA bus architecture allowing reuse of existing SoC components IBM makes the CoreConnect bus available as a no fee no royalty architecture to tool vendors core IP companies and chip development companies As such it is licensed by over 1500 electronics companies such as Cadence Ericsson Lucent Nokia Siemens and Synopsys The CoreConnect is an integral part of IBM s embedded offerings and is used extensively in their PowerPC 4x0 based designs In the past Xilinx was using CoreConnect as the infrastructure for all of their embedded processor designs Processor Local Bus PLB editGeneral processor local bus Synchronous nonmultiplexed bus Separate Read Write data buses Supports concurrent Read Writes Multimaster programmable priority arbitrated bus 32 bit up to 64 bit address 32 64 128 bit implementations to 256 bit 66 133 183 MHz 32 64 128 bit Pipelined supports early split transactions Overlapped arbitration last cycle Supports fixed variable length bursts Bus locking High bandwidth capabilities up to 2 9 GB s On chip Peripheral Bus OPB editPeripheral bus for slower devices Synchronous nonmultiplexed bus Multimaster arbitrated bus Up to a 64 bit address bus Separate 32 bit Read Write buses Pipelined transactions Overlapped arbitration last cycle Supports bursts Dynamic bus sizing 8 16 32 bit devices Single cycle data transfers Bus locking parking Device Control Register DCR bus editThis bus provides fully synchronous movement of GPR data between CPU and slave logic functions as a synchronous nonmultiplexed bus has separate buses to read and to write data consists of a single master multiple slave bus includes a 10 bit address bus features 32 bit data buses uses two cycle minimum Read Write cycles utilizes distributed multiplexer architecture supports 8 16 and 32 bit devices performs single cycle data transfersExternal links editCoreConnect bus architecture IBM com CoreConnect Technology Xilinx com CoreConnect licensing IBM com CoreConnect The On Chip Bus System ElectronicDesign com Device Control Register Bus 3 5 Architecture Specifications Retrieved from https en wikipedia org w index php title CoreConnect amp oldid 1192998115, wikipedia, wiki, book, books, library,
