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Comparison of ARM processors

January 01, 1970

This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

ARMv7-A edit

This is a table comparing 32-bit central processing units that implement the ARMv7-A (A means Application[1]) instruction set architecture and mandatory or optional extensions of it, the last AArch32.

Core Decode
width		 Execution
ports		 Pipeline
depth		 Out-of-order execution FPU Pipelined
VFP		 FPU
registers		 NEON
(SIMD)		 big.LITTLE
role		 Virtualization[2] Process
technology		 L0
cache		 L1
cache		 L2
cache		 Core
configurations		 Speed
per
core
(DMIPS
/ MHz)		 ARM part number
(in the main ID register)
ARM Cortex-A5 1 8 No VFPv4 (optional) 16 × 64-bit 64-bit wide (optional) No No 40/28 nm 4–64 KiB / core 1, 2, 4 1.57 0xC05
ARM Cortex-A7 2 5[3] 8 No VFPv4 Yes 16 × 64-bit 64-bit wide LITTLE Yes[4] 40/28 nm 8–64 KiB / core up to 1 MiB (optional) 1, 2, 4, 8 1.9 0xC07
ARM Cortex-A8 2 2[5] 13 No VFPv3 No 32 × 64-bit 64-bit wide No No 65/55/45 nm 32 KiB + 32 KiB 256 or 512 (typical) KiB 1 2.0 0xC08
ARM Cortex-A9 2 3[6] 8–11[7] Yes VFPv3 (optional) Yes (16 or 32) × 64-bit 64-bit wide (optional) Companion Core No[7] 65/45/40/32/28 nm 32 KiB + 32 KiB 1 MiB 1, 2, 4 2.5 0xC09
ARM Cortex-A12 2 11 Yes VFPv4 Yes 32 × 64-bit 128-bit wide No[8] Yes 28 nm 32–64 KiB + 32 KiB 256 KiB, to 8 MiB 1, 2, 4 3.0 0xC0D
ARM Cortex-A15 3 8[3] 15/17-25 Yes VFPv4 Yes 32 × 64-bit 128-bit wide big Yes[9] 32/28/20 nm 32 KiB + 32 KiB per core up to 4 MiB per cluster, up to 8 MiB per chip 2, 4, 8 (4×2) 3.5 to 4.01 0xC0F
ARM Cortex-A17 2[10] 11+ Yes VFPv4 Yes 32 × 64-bit 128-bit wide big Yes 28 nm 32 KiB + 32 KiB per core 256 KiB, up to 8 MiB up to 4 4.0 0xC0E
Qualcomm Scorpion 2 3[11] 10 Yes (FXU&LSU only)[12] VFPv3 Yes 128-bit wide No 65/45 nm 32 KiB + 32 KiB 256 KiB (single-core)
512 KiB (dual-core) 		1, 2 2.1 0x00F
Qualcomm Krait[13] 3 7 11 Yes VFPv4[14] Yes 128-bit wide No 28 nm 4 KiB + 4 KiB direct mapped 16 KiB + 16 KiB 4-way set associative 1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core) 2, 4 3.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450) 		0x04D

0x06F
Swift 3 5 12 Yes VFPv4 Yes 32 × 64-bit 128-bit wide No 32 nm 32 KiB + 32 KiB 1 MiB 2 3.5 ?
Core Decode
width 		Execution
ports 		Pipeline
depth 		Out-of-order execution FPU Pipelined
VFP 		FPU
registers 		NEON
(SIMD) 		big.LITTLE
role 		Virtualization[2] Process
technology 		L0
cache 		L1
cache 		L2
cache 		Core
configurations 		Speed
per
core
(DMIPS
/ MHz) 		ARM part number
(in the main ID register)

ARMv8-A edit

This is a table of 64/32-bit central processing units that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Company Core Released Revision Decode Pipeline
depth 		Out-of-order
execution 		Branch
prediction 		big.LITTLE role Exec.
ports 		SIMD Fab
(in nm) 		Simult. MT L0 cache L1 cache
Instr + Data
(in KiB) 		L2 cache L3 cache Core
configu-
rations 		Speed per core (DMIPS/
MHz[note 1]) 		Clock rate ARM part number (in the main ID register)
Have it Entries
ARM Cortex-A32 (32-bit)[15] 2017 ARMv8.0-A
(only 32-bit)		 2-wide 8 No 0 ? LITTLE ? ? 28[16] No No 8–64 + 8–64 0–1 MiB No 1–4+ 2.3 ? 0xD01
Cortex-A34 (64-bit)[17] 2019 ARMv8.0-A
(only 64-bit)		 2-wide 8 No 0 ? LITTLE ? ? ? No No 8–64 + 8–64 0–1 MiB No 1–4+ ? ? 0xD02
Cortex-A35[18] 2017 ARMv8.0-A 2-wide[19] 8 No 0 Yes LITTLE ? ? 28 / 16 /
14 / 10		 No No 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.7[20]-1.85 ? 0xD04
Cortex-A53[21] 2014 ARMv8.0-A 2-wide 8 No 0 Conditional+
Indirect branch
prediction		 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 10		 No No 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24[22] ? 0xD03
Cortex-A55[23] 2017 ARMv8.2-A 2-wide 8 No 0 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 12 / 10 / 5[24] 		No No 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ 2.65[25] ? 0xD05
Cortex-A57[26] 2013 ARMv8.0-A 3-wide 15 Yes
3-wide dispatch		 ? ? big 8 ? 28 / 20 /
16[27] / 14		 No No 48 + 32 0.5–2 MiB No 1–4+ 4.1[20]-4.8 ? 0xD07
Cortex-A65[28] 2019 ARMv8.2-A
(only 64-bit)		 2-wide 10-12 Yes
4-wide dispatch 		Two-level ? 9 ? SMT2 No 32–64 + 32–64 KiB 0, 64–256 KiB 0, 0.5–4 MiB 1-8 ? ? 0xD06
Cortex-A65AE[29] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? SMT2 No 32–64 + 32–64 KiB 64–256 KiB 0, 0.5–4 MiB 1–8 ? ? 0xD43
Cortex-A72[30] 2015 ARMv8.0-A 3-wide 15 Yes
5-wide dispatch 		Two-level big 8 28 / 16 No No 48 + 32 0.5–4 MiB No 1–4+ 4.7[22]-6.3[31] ? 0xD08
Cortex-A73[32] 2016 ARMv8.0-A 2-wide 11–12 Yes
4-wide dispatch 		Two-level big 7 28 / 16 / 10 No No 64 + 32/64 1–8 MiB No 1–4+ 4.8[20]–8.5[31] ? 0xD09
Cortex-A75[23] 2017 ARMv8.2-A 3-wide 11–13 Yes
6-wide dispatch 		Two-level big 8? 2*128b 28 / 16 / 10 No No 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ 6.1[20]–9.5[31] ? 0xD0A
Cortex-A76[33] 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		128 Two-level big 8 2*128b 10 / 7 No No 64 + 64 256–512 KiB/core 1–4 MiB 1–4 6.4 ? 0xD0B
Cortex-A76AE[34] 2018 ARMv8.2-A ? ? Yes 128 Two-level big ? ? No No ? ? ? ? ? ? 0xD0E
Cortex-A77[35] 2019 ARMv8.2-A 4-wide 11–13 Yes
10-wide dispatch 		160 Two-level big 12 2*128b 7 No 1.5K entries 64 + 64 256–512 KiB/core 1–4 MiB 1–4 7.3[20][36] ? 0xD0D
Cortex-A78[37][38] 2020 ARMv8.2-A 4-wide Yes 160 Yes big 13 2*128b No 1.5K entries 32/64 + 32/64 256–512 KiB/core 1–4 MiB 1–4 7.6-8.2 ? 0xD41
Cortex-X1[39] 2020 ARMv8.2-A 5-wide[39] ? Yes 224 Yes big 15 4*128b No 3K entries 64 + 64 up to 1 MiB[39] up to 8 MiB[39] custom[39] 10-11 ? 0xD44
Apple Cyclone[40] 2013 ARMv8.0-A 6-wide[41] 16[41] Yes[41] 192 Yes No 9[41] 28[42] No No 64 + 64[41] 1 MiB[41] 4 MiB[41] 2[43] ? 1.3–1.4 GHz
Typhoon 2014 ARMv8.0‑A 6-wide[44] 16[44] Yes[44] Yes No 9 20 No No 64 + 64[41] 1 MiB[44] 4 MiB[41] 2, 3 (A8X) ? 1.1–1.5 GHz
Twister 2015 ARMv8.0‑A 6-wide[44] 16[44] Yes[44] Yes No 9 16 / 14 No No 64 + 64[44] 3 MiB[44] 4 MiB[44]
No (A9X)		 2 ? 1.85–2.26 GHz
Hurricane 2016 ARMv8.0‑A 6-wide[45] 16 Yes "big" (In A10/A10X paired with "LITTLE" Zephyr
cores) 		9 3*128b 16 (A10)
10 (A10X) 		No No 64 + 64[46] 3 MiB[46] (A10)
8 MiB (A10X) 		4 MiB[46] (A10)
No (A10X) 		2x Hurricane (A10)
3x Hurricane (A10X) 		? 2.34–2.36 GHz
Zephyr ARMv8.0‑A 3-wide 12 Yes LITTLE 5 16 (A10)
10 (A10X) 		No No 32 + 32[47] 1 MiB 4 MiB[46] (A10)
No (A10X) 		2x Zephyr (A10)
3x Zephyr (A10X) 		? 1.09–1.3 GHz
Monsoon 2017 ARMv8.2‑A[48] 7-wide 16 Yes "big" (In Apple A11 paired with "LITTLE" Mistral
cores) 		11 3*128b 10 No No 64 + 64[47] 8 MiB No 2x Monsoon ? 2.39 GHz
Mistral ARMv8.2‑A[48] 3-wide 12 Yes LITTLE 5 10 No No 32 + 32[47] 1 MiB No 4× Mistral ? 1.19 GHz
Vortex 2018 ARMv8.3‑A[49] 7-wide 16 Yes "big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores) 		11 3*128b 7 No No 128 + 128[47] 8 MiB No 2x Vortex (A12)
4x Vortex (A12X/A12Z) 		? 2.49 GHz
Tempest ARMv8.3‑A[49] 3-wide 12 Yes LITTLE 5 7 No No 32 + 32[47] 2 MiB No 4x Tempest ? 1.59 GHz
Lightning 2019 ARMv8.4‑A[50] 8-wide 16 Yes 560 "big" (In Apple A13 paired with "LITTLE" Thunder
cores) 		11 3*128b 7 No No 128 + 128[51] 8 MiB No 2x Lightning ? 2.65 GHz
Thunder ARMv8.4‑A[50] 3-wide 12 Yes LITTLE 5 7 No No 96 + 48[52] 4 MiB No 4x Thunder ? 1.8 GHz
Firestorm 2020 ARMv8.4-A[53] 8-wide[54] Yes 630[55] "big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
cores) 		14 4*128b 5 No 192 + 128 8 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra) 		No 2x Firestorm (A14)
4x Firestorm (M1)

6x or 8x Firestorm (M1 Pro)
8x Firestorm (M1 Max)
16x Firestorm (M1 Ultra)

? 3.0–3.23 GHz
Icestorm ARMv8.4-A[53] 4-wide Yes 110 LITTLE 7 2*128b 5 No 128 + 64 4 MiB
8 MiB (M1 Ultra) 		No 4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra) 		? 1.82–2.06 GHz
Avalanche 2021 ARMv8.6‑A[53] 8-wide Yes "big" (In Apple A15 and Apple M2/M2 Pro/M2 Max/M2 Ultra paired with "LITTLE" Blizzard
cores) 		14 4*128b 5 No 192 + 128 12 MiB (A15)
16 MiB (M2)
32 MiB (M2 Pro/M2 Max)
64 MiB (M2 Ultra) 		No 2x Avalanche (A15)
4x Avalanche (M2)
6x or 8x Avalanche (M2 Pro)

8x Avalanche (M2 Max)
16x Avalanche (M2 Ultra)

? 2.93–3.49 GHz
Blizzard ARMv8.6‑A[53] 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB
8 MiB (M2 Ultra) 		No 4x Blizzard ? 2.02–2.42 GHz
Everest 2022 ARMv8.6‑A[53] 8-wide Yes "big" (In Apple A16 paired with "LITTLE" Sawtooth
cores) 		14 4*128b 5 No 192 + 128 16 MiB No 2x Everest ? 3.46 GHz
Sawtooth ARMv8.6‑A[53] 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB No 4x Sawtooth ? 2.02 GHz
Nvidia Denver[56][57] 2014 ARMv8‑A 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops 		13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW. 		Direct+
Indirect branch
prediction 		No 7 28 No No 128 + 64 2 MiB No 2 ? ?
Denver 2[58] 2016 ARMv8‑A ? 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW. 		Direct+
Indirect branch
prediction 		"Super" Nvidia's own implementation ? 16 No No 128 + 64 2 MiB No 2 ? ?
Carmel 2018 ARMv8.2‑A ? Direct+
Indirect branch
prediction 		? 12 No No 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) 6.5-7.4 ?
Cavium ThunderX[59][60] 2014 ARMv8-A 2-wide 9[60] Yes[59] Two-level ? 28 No No 78 + 32[61][62] 16 MiB[61][62] No 8–16, 24–48 ? ?
ThunderX2
[63](ex. Broadcom Vulcan[64]) 		2018[65] ARMv8.1-A
[66]		 4-wide
"4 μops"[67][68]		 ? Yes[69] Multi-level ? ? 16[70] SMT4 No 32 + 32
(data 8-way)		 256 KiB
per core[71]		 1 MiB
per core[71]		 16–32[71] ? ?
Marvell ThunderX3 2020[72] ARMv8.3+[72] 8-wide ? Yes
4-wide dispatch 		Multi-level ? 7 7[72] SMT4[72] ? 64 + 32 512 KiB
per core		 90 MiB 60 ? ?
Applied

Micro

Helix 2014 ? ? ? ? ? ? ? 40 / 28 No No 32 + 32 (per core;
write-through
w/parity)[73]		 256 KiB shared
per core pair (with ECC)		 1 MiB/core 2, 4, 8 ? ?
X-Gene 2013 ? 4-wide 15 Yes ? ? ? 40[74] No No 8 MiB 8 4.2 ?
X-Gene 2 2015 ? 4-wide 15 Yes ? ? ? 28[75] No No 8 MiB 8 4.2 ?
X-Gene 3[75] 2017 ? ? ? ? ? ? ? 16 No No ? ? 32 MiB 32 ? ?
Qualcomm Kryo 2015 ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation		 ? 14[76] No No 32+24[77] 0.5–1 MiB 2+2 6.3 ?
Kryo 200 2016 ARMv8-A 2-wide 11–12 Yes
7-wide dispatch 		Two-level big 7 14 / 11 / 10 / 6[78] No No 64 + 32/64? 512 KiB/Gold Core No 4 ? 1.8–2.45 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 8–64? + 8–64? 256 KiB/Silver Core 4 ? 1.8–1.9 GHz
Kryo 300 2017 ARMv8.2-A 3-wide 11–13 Yes
8-wide dispatch 		Two-level big 8 10[78] No No 64+64[78] 256 KiB/Gold Core 2 MiB 2, 4 ? 2.0–2.95 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 28 16–64? + 16–64? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 400 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 8 11 / 8 / 7 No No 64 + 64 512 KiB/Gold Prime

256 KiB/Gold

2 MiB 2, 1+1, 4, 1+3 ? 2.0–2.96 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 16–64? + 16–64? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 500 2019 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 8 / 7 No ? 512 KiB/Gold Prime

256 KiB/Gold

3 MiB 2, 1+3 ? 2.0–3.2 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 ? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 600 2020 ARMv8.4-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 6 / 5 No ? 64 + 64 1024 KiB/Gold Prime

512 KiB/Gold

4 MiB 2, 1+3 ? 2.2–3.0 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 ? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Falkor[79][80] 2017[81] "ARMv8.1-A features";[80] AArch64 only (not 32-bit)[80] 4-wide 10–15 Yes
8-wide dispatch 		Yes ? 8 10 No 24 KiB 88[80] + 32 500KiB 1.25MiB 40–48 ? ?
Samsung M1[82][83] 2016 ARMv8-A 4-wide 13[84] Yes
9-wide dispatch[85] 		96 big 8 14 No No 64 + 32 2 MiB[86] No 4 ? 2.6 GHz
M2[82][83] 2017 ARMv8-A 4-wide 100 Two-level big 10 No No 64 + 64 2 MiB No 4 ? 2.3 GHz
M3[84][87] 2018 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch 		228 Two-level big 12 10 No No 64 + 64 512 KiB per core 4096KB 4 ? 2.7 GHz
M4[88] 2019 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch 		228 Two-level big 12 8 / 7 No No 64 + 64 512 KiB per core 3072KB 2 ? 2.73 GHz
M5[89] 2020 ARMv8.2-A 6-wide Yes
12-wide dispatch 		228 Two-level big 7 No No 64 + 64 512 KiB per core 3072KB 2 ? 2.73 GHz
Fujitsu A64FX[90][91] 2019 ARMv8.2-A 4/2-wide 7+ Yes
5-way? 		Yes n/a 8+ 2*512b[92] 7 No No 64 + 64 8MiB per 12+1 cores No 48+4 ? 1.9 GHz+
HiSilicon TaiShan V110[93] 2019 ARMv8.2-A 4-wide ? Yes n/a 8 7 No No 64 + 64 512 KiB per core 1 MiB per core ? ? ?
Company Core Released Revision Decode Pipeline
depth 		Out-of-order
execution 		Branch
prediction 		big.LITTLE role Exec.
ports 		SIMD Fab
(in nm) 		Simult. MT L0 cache L1 cache
Instr + Data
(in KiB) 		L2 cache L3 cache Core
configu-
rations 		Speed per core (DMIPS/
MHz[note 1]) 		Clock rate ARM part number (in the main ID register)

See also edit

Notes edit

  1. ^ a b As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

References edit

  1. ^ "ARM V7 Differences". infocenter.arm.com. ARM Information Center. Retrieved 1 June 2016.
  2. ^ a b "ARM processor hardware virtualization support". arm.com. ARM Holdings. Retrieved 1 June 2016.
  3. ^ a b (PDF). arm.com. ARM Holdings. Archived from the original (PDF) on 17 October 2013. Retrieved 6 August 2014.
  4. ^ "Cortex-A7 processor". arm.com. ARM Holdings. Retrieved 1 June 2016.
  5. ^ . processors.wiki.TI.com. Texas Instruments. Archived from the original on 8 August 2014. Retrieved 6 August 2014.
  6. ^ (PDF). arm.com. ARM Holdings. Archived from the original (PDF) on 17 November 2014. Retrieved 6 August 2014.
  7. ^ a b "Cortex-A9 processor". arm.com. ARM Holdings. Retrieved 15 September 2014.
  8. ^ "ARM Cortex-A17 / Cortex-A12 processor update – Architectures and Processors blog – Arm Community blogs – Arm Community".
  9. ^ "Cortex-A15 processor". arm.com. ARM Holdings. Retrieved 9 August 2016.
  10. ^ "ARM Cortex-A17 MPCore processor technical reference manual" (PDF). infocenter.arm.com. ARM Holdings. Retrieved 18 September 2014.
  11. ^ Klug, Brian (7 October 2011). "Qualcomm's new Snapdragon S4: MSM8960 & Krait architecture explored". anandtech.com. Anandtech. Retrieved 6 August 2014.
  12. ^ Mallia, Lou (2007). (PDF). Archived from the original (PDF) on 26 April 2017. Retrieved 8 May 2014.
  13. ^ "Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored".
  14. ^ "Qualcomm Snapdragon S4 (Krait) Performance Preview – 1.5 GHZ MSM8960 MDP and Adreno 225 Benchmarks".
  15. ^ Frumusanu, Andrei (22 February 2016). "ARM Announces Cortex-A32 IoT and Embedded Processor". Anandtech.com. Retrieved 13 June 2016.
  16. ^ "New Ultra-efficient ARM Cortex-A32 Processor Expands… – ARM". arm.com. Retrieved 1 October 2016.
  17. ^ Ltd, Arm. "Cortex-A34". ARM Developer. Retrieved 10 October 2019.
  18. ^ "Cortex-A35 Processor". ARM. ARM Ltd.
  19. ^ Frumusanu, Andrei. "ARM Announces New Cortex-A35 CPU – Ultra-High Efficiency For Wearables & More".
  20. ^ a b c d e "High Performance Processors, Other Interesting Talks". Phoronix comments. Retrieved 24 January 2024.
  21. ^ "Cortex-A53 Processor". ARM. ARM Ltd.
  22. ^ a b "Processing In Xilinx Devices" (PDF). Digilent documents. Retrieved 24 January 2024.
  23. ^ a b Matt, Humrick (29 May 2017). "Exploring DynamIQ and ARM's New CPUs: Cortex-A75, Cortex-A55". Anandtech.com. Retrieved 29 May 2017.
  24. ^ "Qualcomm Snapdragon 888 5G Mobile Platform". Retrieved 6 January 2021.
  25. ^ Based on 18% perf. increment over Cortex-A53 "Arm Cortex-A55: Efficient performance from edge to cloud". ARM. ARM Ltd.
  26. ^ Smith, Andrei Frumusanu, Ryan. "ARM A53/A57/T760 investigated – Samsung Galaxy Note 4 Exynos Review". anandtech.com. Retrieved 17 June 2019.{{cite web}}: CS1 maint: multiple names: authors list (link)
  27. ^ (Press release). TSMC. 25 September 2014. Archived from the original on 20 February 2015. Retrieved 19 February 2015.
  28. ^ "Cortex-A65 – Arm Developer". ARM Ltd. Retrieved 14 July 2020.
  29. ^ "Cortex-A65AE – Arm Developer". ARM Ltd. Retrieved 26 April 2019.
  30. ^ Frumusanu, Andrei. "ARM Reveals Cortex-A72 Architecture Details". Anandtech. Retrieved 25 April 2015.
  31. ^ a b c "ARM's processor lines" (PDF). users.nik.uni-obuda.hu. November 2018. Retrieved 24 October 2023.
  32. ^ Frumusanu, Andrei (29 May 2016). "The ARM Cortex A73 – Artemis Unveiled". Anandtech.com. Retrieved 31 May 2016.
  33. ^ Frumusanu, Andrei (31 May 2018). "ARM Cortex-A76 CPU Unveiled". Anandtech. Retrieved 1 June 2018.
  34. ^ "Cortex-A76AE – Arm Developer". ARM Ltd. Retrieved 14 July 2020.
  35. ^ Schor, David (26 May 2019). "Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance". WikiChip Fuse. Retrieved 17 June 2019.
  36. ^ According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017
  37. ^ "Arm Unveils the Cortex-A78: When Less Is More". WikiChip Fuse. 26 May 2020. Retrieved 28 May 2020.
  38. ^ Ltd, Arm. "Cortex-A78". ARM Developer. Retrieved 28 May 2020.
  39. ^ a b c d e "Introducing the Arm Cortex-X Custom program". community.arm.com. Retrieved 28 May 2020.
  40. ^ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: The Move to 64-bit". AnandTech. Retrieved 3 July 2014.
  41. ^ a b c d e f g h i Lal Shimpi, Anand (31 March 2014). "Apple's Cyclone Microarchitecture Detailed". AnandTech. Retrieved 3 July 2014.
  42. ^ Dixon-Warren, Sinjin (20 January 2014). . Chipworks. Archived from the original on 6 April 2014. Retrieved 3 July 2014.
  43. ^ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: A7 SoC Explained". AnandTech. Retrieved 3 July 2014.
  44. ^ a b c d e f g h i j Ho, Joshua; Smith, Ryan (2 November 2015). "The Apple iPhone 6s and iPhone 6s Plus Review". AnandTech. Retrieved 13 February 2016.
  45. ^ "Apple had shifted the microarchitecture in Hurricane (A10) from a 6-wide decode from to a 7-wide decode". AnandTech. 5 October 2018.
  46. ^ a b c d "Apple A10 Fusion". system-on-a-chip.specout.com. Retrieved 1 October 2016.[permanent dead link]
  47. ^ a b c d e "Measured and Estimated Cache Sizes". AnandTech. 5 October 2018.
  48. ^ a b "Apple A11 New Instruction Set Extensions" (PDF). Apple Inc. 8 June 2018.
  49. ^ a b . Jonathan Levin, @Morpheus. 12 September 2018. Archived from the original on 10 October 2018. Retrieved 8 October 2018.
  50. ^ a b "A13 has ARMv8.4, apparently (LLVM project sources, thanks, @Longhorn)". Jonathan Levin, @Morpheus. 13 March 2020.
  51. ^ "The Apple A13 SoC: Lightning & Thunder". AnandTech. 16 October 2019.
  52. ^ "The A13's Memory Subsystem: Faster L2, More SLC BW". AnandTech. 16 October 2019.
  53. ^ a b c d e f "llvm-project/llvm/lib/Target/AArch64/AArch64.td at main - llvm/llvm-project - GitHub". github.com. Retrieved 3 July 2023.
  54. ^ "Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14". AnandTech. 10 November 2020.
  55. ^ Frumusanu, Andrei. "Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14". anandtech.com. Retrieved 25 November 2020.
  56. ^ Stam, Nick (11 August 2014). . NVidia. Archived from the original on 12 August 2014. Retrieved 11 August 2014.
  57. ^ Gwennap, Linley. "Denver Uses Dynamic Translation to Outperform Mobile Rivals". The Linley Group. Retrieved 24 April 2015.
  58. ^ Ho, Joshua (25 August 2016). "Hot Chips 2016: NVIDIA Discloses Tegra Parker Details". Anandtech. Retrieved 25 August 2016.
  59. ^ a b De Gelas, Johan (16 December 2014). "ARM Challenging Intel in the Server Market". Anandtech. Retrieved 8 March 2017.
  60. ^ a b De Gelas, Johan (15 June 2016). "Investigating the Cavium ThunderX". Anandtech. Retrieved 8 March 2017.
  61. ^ a b "64-bit Cortex Platform To Take on x86 Servers in the Cloud". electronic design. 5 June 2014. Retrieved 7 February 2015.
  62. ^ a b "ThunderX_CP™ Family of Workload Optimized Compute Processors" (PDF). Cavium. 2014. Retrieved 7 February 2015.
  63. ^ "A Look at Cavium's New High-Performance ARM Microprocessors and the Isambard Supercomputer". WikiChip Fuse. 3 June 2018. Retrieved 17 June 2019.
  64. ^ "⚙ D30510 Vulcan is now ThunderX2T99". reviews.llvm.org.
  65. ^ Kennedy, Patrick (7 May 2018). "Cavium ThunderX2 256 Thread Arm Platforms Hit General Availability". Retrieved 10 May 2018.
  66. ^ "⚙ D21500 [AARCH64] Add support for Broadcom Vulcan". reviews.llvm.org.
  67. ^ Hayes, Eric (7 April 2014). "IDC HPC USER FORUM" (PDF). hpcuserforum.com.
  68. ^ "The Linley Group – Processor Conference 2013". linleygroup.com.
  69. ^ "ThunderX2 ARM Processors- A Game Changing Family of Workload Optimized Processors for Data Center and Cloud Applications – Cavium". cavium.com.
  70. ^ "Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture". Broadcom. 15 October 2013. Retrieved 11 August 2014.
  71. ^ a b c Kennedy, Patrick (9 May 2018). "Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option". Serve the Home. Retrieved 10 May 2018.
  72. ^ a b c d Frumusanu, Andrei (16 March 2020). "Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor".
  73. ^ Ganesh T S (3 October 2014). "ARMv8 Goes Embedded with Applied Micro's HeliX SoCs". AnandTech. Retrieved 9 October 2014.
  74. ^ Morgan, Timothy Prickett (12 August 2014). "Applied Micro Plots Out X-Gene ARM Server Future". Enterprisetech. Retrieved 9 October 2014.
  75. ^ a b De Gelas, Johan (15 March 2017). "AppliedMicro's X-Gene 3 SoC Begins Sampling". Anandtech. Retrieved 15 March 2017.
  76. ^ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2 September 2015. Retrieved 6 September 2015.
  77. ^ Frumusanu, Ryan Smith, Andrei. "The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo".{{cite web}}: CS1 maint: multiple names: authors list (link)
  78. ^ a b c Smith, Andrei Frumusanu, Ryan. "The Snapdragon 845 Performance Preview: Setting the Stage for Flagship Android 2018". Retrieved 11 June 2018.{{cite news}}: CS1 maint: multiple names: authors list (link)
  79. ^ Shilov, Anton (16 December 2016). "Qualcomm Demos 48-Core Centriq 2400 SoC in Action, Begins Sampling". Anandtech. Retrieved 8 March 2017. In 2015, Qualcomm teamed up with Xilinx and Mellanox to ensure that its server SoCs are compatible with FPGA-based accelerators and data-center connectivity solutions (the fruits of this partnership will likely emerge in 2018 at best).
  80. ^ a b c d Cutress, Ian (20 August 2017). "Analyzing Falkor's Microarchitecture". Anandtech. Retrieved 21 August 2017. The CPU cores, code named Falkor, will be ARMv8.0 compliant although with ARMv8.1 features, allowing software to potentially seamlessly transition from other ARM environments (or need a recompile). The Centriq 2400 family is set to be AArch64 only, without support for AArch32: Qualcomm states that this saves some power and die area, but that they primarily chose this route because the ecosystems they are targeting have already migrated to 64-bit. Qualcomm's Chris Bergen, Senior Director of Product Management for the Centriq 2400, stated that the majority of new and upcoming companies have started off with 64-bit as their base in the data center, and not even considering 32-bit, which is a reason for the AArch64-only choice here. [..] Micro-op cache / L0 I-cache with Way prediction [..] The L1 I-cache is 64KB, which is similar to other ARM architecture core designs, and also uses 64-byte lines but with an 8-way associativity. To software, as the L0 is transparent, the L1 I-cache will show as an 88KB cache.
  81. ^ Shrout, Ryan (8 November 2017). "Qualcomm Centriq 2400 Arm-based Server Processor Begins Commercial Shipment". PC Per. Retrieved 8 November 2017.
  82. ^ a b Ho, Joshua. "Hot Chips 2016: Exynos M1 Architecture Disclosed".
  83. ^ a b Frumusanu, Andrei. "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU".
  84. ^ a b Frumusanu, Andrei (23 January 2018). "The Samsung Exynos M3 – 6-wide Decode with 50%+ IPC Increase". Anandtech. Retrieved 25 January 2018.
  85. ^ Frumusanu, Andrei. "Hot Chips 2016: Exynos M1 Architecture Disclosed". Anandtech. Retrieved 29 May 2017.
  86. ^ "'Neural network' spotted deep inside Samsung's Galaxy S7 silicon brain". The Register.
  87. ^ Frumusanu, Andrei. "Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive". anandtech.com. Retrieved 17 June 2019.
  88. ^ Schor, David (14 January 2019). "Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End". WikiChip Fuse. Retrieved 17 June 2019.
  89. ^ Frumusanu, Andrei. "ISCA 2020: Evolution of the Samsung Exynos CPU Microarchitecture". anandtech.com. Retrieved 24 January 2021.
  90. ^ Fujitsu High Performance CPU for the Post-K Computer (PDF), 21 July 2018, retrieved 16 September 2019
  91. ^ Arm A64fx and Post-K: Game Changing CPU & Supercomputer for HPC and its Convergence of with Big Data / AI (PDF), 3 April 2019, retrieved 16 September 2019
  92. ^ "Fujitsu Successfully Triples the Power Output of Gallium-Nitride Transistors – Fujitsu Global". fujitsu.com. Retrieved 23 November 2020.
  93. ^ Schor, David (3 May 2019). "Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen". WikiChip Fuse. Retrieved 13 December 2019.

January 01, 1970
comparison, processors, this, article, needs, additional, citations, verification, relevant, discussion, found, talk, page, please, help, improve, this, article, adding, citations, reliable, sources, unsourced, material, challenged, removed, find, sources, new. This article needs additional citations for verification Relevant discussion may be found on the talk page Please help improve this article by adding citations to reliable sources Unsourced material may be challenged and removed Find sources Comparison of ARM processors news newspapers books scholar JSTOR June 2014 Learn how and when to remove this message This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings ARM Cortex A and 3rd parties It does not include ARM Cortex R ARM Cortex M or legacy ARM cores Contents 1 ARMv7 A 2 ARMv8 A 3 See also 4 Notes 5 ReferencesARMv7 A editThis is a table comparing 32 bit central processing units that implement the ARMv7 A A means Application 1 instruction set architecture and mandatory or optional extensions of it the last AArch32 This list is incomplete you can help by adding missing items February 2014 Core Decodewidth Executionports Pipelinedepth Out of order execution FPU PipelinedVFP FPUregisters NEON SIMD big LITTLErole Virtualization 2 Processtechnology L0cache L1cache L2cache Coreconfigurations Speedpercore DMIPS MHz ARM part number in the main ID register ARM Cortex A5 1 8 No VFPv4 optional 16 64 bit 64 bit wide optional No No 40 28 nm 4 64 KiB core 1 2 4 1 57 0xC05 ARM Cortex A7 2 5 3 8 No VFPv4 Yes 16 64 bit 64 bit wide LITTLE Yes 4 40 28 nm 8 64 KiB core up to 1 MiB optional 1 2 4 8 1 9 0xC07 ARM Cortex A8 2 2 5 13 No VFPv3 No 32 64 bit 64 bit wide No No 65 55 45 nm 32 KiB 32 KiB 256 or 512 typical KiB 1 2 0 0xC08 ARM Cortex A9 2 3 6 8 11 7 Yes VFPv3 optional Yes 16 or 32 64 bit 64 bit wide optional Companion Core No 7 65 45 40 32 28 nm 32 KiB 32 KiB 1 MiB 1 2 4 2 5 0xC09 ARM Cortex A12 2 11 Yes VFPv4 Yes 32 64 bit 128 bit wide No 8 Yes 28 nm 32 64 KiB 32 KiB 256 KiB to 8 MiB 1 2 4 3 0 0xC0D ARM Cortex A15 3 8 3 15 17 25 Yes VFPv4 Yes 32 64 bit 128 bit wide big Yes 9 32 28 20 nm 32 KiB 32 KiB per core up to 4 MiB per cluster up to 8 MiB per chip 2 4 8 4 2 3 5 to 4 01 0xC0F ARM Cortex A17 2 10 11 Yes VFPv4 Yes 32 64 bit 128 bit wide big Yes 28 nm 32 KiB 32 KiB per core 256 KiB up to 8 MiB up to 4 4 0 0xC0E Qualcomm Scorpion 2 3 11 10 Yes FXU amp LSU only 12 VFPv3 Yes 128 bit wide No 65 45 nm 32 KiB 32 KiB 256 KiB single core 512 KiB dual core 1 2 2 1 0x00F Qualcomm Krait 13 3 7 11 Yes VFPv4 14 Yes 128 bit wide No 28 nm 4 KiB 4 KiB direct mapped 16 KiB 16 KiB 4 way set associative 1 MiB 8 way set associative dual core 2 MiB quad core 2 4 3 3 Krait 200 3 39 Krait 300 3 39 Krait 400 3 51 Krait 450 0x04D0x06F Swift 3 5 12 Yes VFPv4 Yes 32 64 bit 128 bit wide No 32 nm 32 KiB 32 KiB 1 MiB 2 3 5 Core Decodewidth Executionports Pipelinedepth Out of order execution FPU PipelinedVFP FPUregisters NEON SIMD big LITTLErole Virtualization 2 Processtechnology L0cache L1cache L2cache Coreconfigurations Speedpercore DMIPS MHz ARM part number in the main ID register ARMv8 A editThis is a table of 64 32 bit central processing units that implement the ARMv8 A instruction set architecture and mandatory or optional extensions of it Most chips support the 32 bit ARMv7 A for legacy applications All chips of this type have a floating point unit FPU that is better than the one in older ARMv7 A and NEON SIMD chips Some of these chips have coprocessors also include cores from the older 32 bit architecture ARMv7 Some of the chips are SoCs and can combine both ARM Cortex A53 and ARM Cortex A57 such as the Samsung Exynos 7 Octa This list is incomplete you can help by adding missing items May 2014 Company Core Released Revision Decode Pipelinedepth Out of orderexecution Branchprediction big LITTLE role Exec ports SIMD Fab in nm Simult MT L0 cache L1 cacheInstr Data in KiB L2 cache L3 cache Coreconfigu rations Speed per core DMIPS MHz note 1 Clock rate ARM part number in the main ID register Have it Entries ARM Cortex A32 32 bit 15 2017 ARMv8 0 A only 32 bit 2 wide 8 No 0 LITTLE 28 16 No No 8 64 8 64 0 1 MiB No 1 4 2 3 0xD01 Cortex A34 64 bit 17 2019 ARMv8 0 A only 64 bit 2 wide 8 No 0 LITTLE No No 8 64 8 64 0 1 MiB No 1 4 0xD02 Cortex A35 18 2017 ARMv8 0 A 2 wide 19 8 No 0 Yes LITTLE 28 16 14 10 No No 8 64 8 64 0 128 KiB 1 MiB No 1 4 1 7 20 1 85 0xD04 Cortex A53 21 2014 ARMv8 0 A 2 wide 8 No 0 Conditional Indirect branchprediction big LITTLE 2 28 20 16 14 10 No No 8 64 8 64 128 KiB 2 MiB No 1 4 2 24 22 0xD03 Cortex A55 23 2017 ARMv8 2 A 2 wide 8 No 0 big LITTLE 2 28 20 16 14 12 10 5 24 No No 16 64 16 64 0 256 KiB core 0 4 MiB 1 8 2 65 25 0xD05 Cortex A57 26 2013 ARMv8 0 A 3 wide 15 Yes 3 wide dispatch big 8 28 20 16 27 14 No No 48 32 0 5 2 MiB No 1 4 4 1 20 4 8 0xD07 Cortex A65 28 2019 ARMv8 2 A only 64 bit 2 wide 10 12 Yes4 wide dispatch Two level 9 SMT2 No 32 64 32 64 KiB 0 64 256 KiB 0 0 5 4 MiB 1 8 0xD06 Cortex A65AE 29 2019 ARMv8 2 A Yes Two level 2 SMT2 No 32 64 32 64 KiB 64 256 KiB 0 0 5 4 MiB 1 8 0xD43 Cortex A72 30 2015 ARMv8 0 A 3 wide 15 Yes 5 wide dispatch Two level big 8 28 16 No No 48 32 0 5 4 MiB No 1 4 4 7 22 6 3 31 0xD08 Cortex A73 32 2016 ARMv8 0 A 2 wide 11 12 Yes 4 wide dispatch Two level big 7 28 16 10 No No 64 32 64 1 8 MiB No 1 4 4 8 20 8 5 31 0xD09 Cortex A75 23 2017 ARMv8 2 A 3 wide 11 13 Yes 6 wide dispatch Two level big 8 2 128b 28 16 10 No No 64 64 256 512 KiB core 0 4 MiB 1 8 6 1 20 9 5 31 0xD0A Cortex A76 33 2018 ARMv8 2 A 4 wide 11 13 Yes 8 wide dispatch 128 Two level big 8 2 128b 10 7 No No 64 64 256 512 KiB core 1 4 MiB 1 4 6 4 0xD0B Cortex A76AE 34 2018 ARMv8 2 A Yes 128 Two level big No No 0xD0E Cortex A77 35 2019 ARMv8 2 A 4 wide 11 13 Yes 10 wide dispatch 160 Two level big 12 2 128b 7 No 1 5K entries 64 64 256 512 KiB core 1 4 MiB 1 4 7 3 20 36 0xD0D Cortex A78 37 38 2020 ARMv8 2 A 4 wide Yes 160 Yes big 13 2 128b No 1 5K entries 32 64 32 64 256 512 KiB core 1 4 MiB 1 4 7 6 8 2 0xD41 Cortex X1 39 2020 ARMv8 2 A 5 wide 39 Yes 224 Yes big 15 4 128b No 3K entries 64 64 up to 1 MiB 39 up to 8 MiB 39 custom 39 10 11 0xD44 Apple Cyclone 40 2013 ARMv8 0 A 6 wide 41 16 41 Yes 41 192 Yes No 9 41 28 42 No No 64 64 41 1 MiB 41 4 MiB 41 2 43 1 3 1 4 GHz Typhoon 2014 ARMv8 0 A 6 wide 44 16 44 Yes 44 Yes No 9 20 No No 64 64 41 1 MiB 44 4 MiB 41 2 3 A8X 1 1 1 5 GHz Twister 2015 ARMv8 0 A 6 wide 44 16 44 Yes 44 Yes No 9 16 14 No No 64 64 44 3 MiB 44 4 MiB 44 No A9X 2 1 85 2 26 GHz Hurricane 2016 ARMv8 0 A 6 wide 45 16 Yes big In A10 A10X paired with LITTLE Zephyrcores 9 3 128b 16 A10 10 A10X No No 64 64 46 3 MiB 46 A10 8 MiB A10X 4 MiB 46 A10 No A10X 2x Hurricane A10 3x Hurricane A10X 2 34 2 36 GHz Zephyr ARMv8 0 A 3 wide 12 Yes LITTLE 5 16 A10 10 A10X No No 32 32 47 1 MiB 4 MiB 46 A10 No A10X 2x Zephyr A10 3x Zephyr A10X 1 09 1 3 GHz Monsoon 2017 ARMv8 2 A 48 7 wide 16 Yes big In Apple A11 paired with LITTLE Mistralcores 11 3 128b 10 No No 64 64 47 8 MiB No 2x Monsoon 2 39 GHz Mistral ARMv8 2 A 48 3 wide 12 Yes LITTLE 5 10 No No 32 32 47 1 MiB No 4 Mistral 1 19 GHz Vortex 2018 ARMv8 3 A 49 7 wide 16 Yes big In Apple A12 Apple A12X Apple A12Z paired with LITTLE Tempestcores 11 3 128b 7 No No 128 128 47 8 MiB No 2x Vortex A12 4x Vortex A12X A12Z 2 49 GHz Tempest ARMv8 3 A 49 3 wide 12 Yes LITTLE 5 7 No No 32 32 47 2 MiB No 4x Tempest 1 59 GHz Lightning 2019 ARMv8 4 A 50 8 wide 16 Yes 560 big In Apple A13 paired with LITTLE Thundercores 11 3 128b 7 No No 128 128 51 8 MiB No 2x Lightning 2 65 GHz Thunder ARMv8 4 A 50 3 wide 12 Yes LITTLE 5 7 No No 96 48 52 4 MiB No 4x Thunder 1 8 GHz Firestorm 2020 ARMv8 4 A 53 8 wide 54 Yes 630 55 big In Apple A14 and Apple M1 M1 Pro M1 Max M1 Ultra paired with LITTLE Icestormcores 14 4 128b 5 No 192 128 8 MiB A14 12 MiB M1 24 MiB M1 Pro M1 Max 48 MiB M1 Ultra No 2x Firestorm A14 4x Firestorm M1 6x or 8x Firestorm M1 Pro 8x Firestorm M1 Max 16x Firestorm M1 Ultra 3 0 3 23 GHz Icestorm ARMv8 4 A 53 4 wide Yes 110 LITTLE 7 2 128b 5 No 128 64 4 MiB8 MiB M1 Ultra No 4x Icestorm A14 M1 2x Icestorm M1 Pro Max 4x Icestorm M1 Ultra 1 82 2 06 GHz Avalanche 2021 ARMv8 6 A 53 8 wide Yes big In Apple A15 and Apple M2 M2 Pro M2 Max M2 Ultra paired with LITTLE Blizzardcores 14 4 128b 5 No 192 128 12 MiB A15 16 MiB M2 32 MiB M2 Pro M2 Max 64 MiB M2 Ultra No 2x Avalanche A15 4x Avalanche M2 6x or 8x Avalanche M2 Pro 8x Avalanche M2 Max 16x Avalanche M2 Ultra 2 93 3 49 GHz Blizzard ARMv8 6 A 53 4 wide Yes LITTLE 8 2 128b 5 No 128 64 4 MiB8 MiB M2 Ultra No 4x Blizzard 2 02 2 42 GHz Everest 2022 ARMv8 6 A 53 8 wide Yes big In Apple A16 paired with LITTLE Sawtoothcores 14 4 128b 5 No 192 128 16 MiB No 2x Everest 3 46 GHz Sawtooth ARMv8 6 A 53 4 wide Yes LITTLE 8 2 128b 5 No 128 64 4 MiB No 4x Sawtooth 2 02 GHz Nvidia Denver 56 57 2014 ARMv8 A 2 wide hardwaredecoder up to7 wide variable length VLIWmicro ops 13 Not if the hardwaredecoder is in use Can be providedby dynamic softwaretranslation into VLIW Direct Indirect branchprediction No 7 28 No No 128 64 2 MiB No 2 Denver 2 58 2016 ARMv8 A 13 Not if the hardwaredecoder is in use Can be providedby dynamic softwaretranslation into VLIW Direct Indirect branchprediction Super Nvidia s own implementation 16 No No 128 64 2 MiB No 2 Carmel 2018 ARMv8 2 A Direct Indirect branchprediction 12 No No 128 64 2 MiB 4 MiB 8 cores 2 8 6 5 7 4 Cavium ThunderX 59 60 2014 ARMv8 A 2 wide 9 60 Yes 59 Two level 28 No No 78 32 61 62 16 MiB 61 62 No 8 16 24 48 ThunderX2 63 ex Broadcom Vulcan 64 2018 65 ARMv8 1 A 66 4 wide 4 mops 67 68 Yes 69 Multi level 16 70 SMT4 No 32 32 data 8 way 256 KiBper core 71 1 MiBper core 71 16 32 71 Marvell ThunderX3 2020 72 ARMv8 3 72 8 wide Yes 4 wide dispatch Multi level 7 7 72 SMT4 72 64 32 512 KiBper core 90 MiB 60 Applied Micro Helix 2014 40 28 No No 32 32 per core write throughw parity 73 256 KiB sharedper core pair with ECC 1 MiB core 2 4 8 X Gene 2013 4 wide 15 Yes 40 74 No No 8 MiB 8 4 2 X Gene 2 2015 4 wide 15 Yes 28 75 No No 8 MiB 8 4 2 X Gene 3 75 2017 16 No No 32 MiB 32 Qualcomm Kryo 2015 ARMv8 A Yes Two level big or LITTLE Qualcomm s own similar implementation 14 76 No No 32 24 77 0 5 1 MiB 2 2 6 3 Kryo 200 2016 ARMv8 A 2 wide 11 12 Yes 7 wide dispatch Two level big 7 14 11 10 6 78 No No 64 32 64 512 KiB Gold Core No 4 1 8 2 45 GHz 2 wide 8 No 0 Conditional Indirect branchprediction LITTLE 2 8 64 8 64 256 KiB Silver Core 4 1 8 1 9 GHz Kryo 300 2017 ARMv8 2 A 3 wide 11 13 Yes 8 wide dispatch Two level big 8 10 78 No No 64 64 78 256 KiB Gold Core 2 MiB 2 4 2 0 2 95 GHz 2 wide 8 No 0 Conditional Indirect branchprediction LITTLE 28 16 64 16 64 128 KiB Silver 4 6 1 7 1 8 GHz Kryo 400 2018 ARMv8 2 A 4 wide 11 13 Yes 8 wide dispatch Yes big 8 11 8 7 No No 64 64 512 KiB Gold Prime 256 KiB Gold 2 MiB 2 1 1 4 1 3 2 0 2 96 GHz 2 wide 8 No 0 Conditional Indirect branchprediction LITTLE 2 16 64 16 64 128 KiB Silver 4 6 1 7 1 8 GHz Kryo 500 2019 ARMv8 2 A 4 wide 11 13 Yes 8 wide dispatch Yes big 8 7 No 512 KiB Gold Prime 256 KiB Gold 3 MiB 2 1 3 2 0 3 2 GHz 2 wide 8 No 0 Conditional Indirect branchprediction LITTLE 2 128 KiB Silver 4 6 1 7 1 8 GHz Kryo 600 2020 ARMv8 4 A 4 wide 11 13 Yes 8 wide dispatch Yes big 6 5 No 64 64 1024 KiB Gold Prime 512 KiB Gold 4 MiB 2 1 3 2 2 3 0 GHz 2 wide 8 No 0 Conditional Indirect branchprediction LITTLE 2 128 KiB Silver 4 6 1 7 1 8 GHz Falkor 79 80 2017 81 ARMv8 1 A features 80 AArch64 only not 32 bit 80 4 wide 10 15 Yes8 wide dispatch Yes 8 10 No 24 KiB 88 80 32 500KiB 1 25MiB 40 48 Samsung M1 82 83 2016 ARMv8 A 4 wide 13 84 Yes 9 wide dispatch 85 96 big 8 14 No No 64 32 2 MiB 86 No 4 2 6 GHz M2 82 83 2017 ARMv8 A 4 wide 100 Two level big 10 No No 64 64 2 MiB No 4 2 3 GHz M3 84 87 2018 ARMv8 2 A 6 wide 15 Yes 12 wide dispatch 228 Two level big 12 10 No No 64 64 512 KiB per core 4096KB 4 2 7 GHz M4 88 2019 ARMv8 2 A 6 wide 15 Yes 12 wide dispatch 228 Two level big 12 8 7 No No 64 64 512 KiB per core 3072KB 2 2 73 GHz M5 89 2020 ARMv8 2 A 6 wide Yes 12 wide dispatch 228 Two level big 7 No No 64 64 512 KiB per core 3072KB 2 2 73 GHz Fujitsu A64FX 90 91 2019 ARMv8 2 A 4 2 wide 7 Yes5 way Yes n a 8 2 512b 92 7 No No 64 64 8MiB per 12 1 cores No 48 4 1 9 GHz HiSilicon TaiShan V110 93 2019 ARMv8 2 A 4 wide Yes n a 8 7 No No 64 64 512 KiB per core 1 MiB per core Company Core Released Revision Decode Pipelinedepth Out of orderexecution Branchprediction big LITTLE role Exec ports SIMD Fab in nm Simult MT L0 cache L1 cacheInstr Data in KiB L2 cache L3 cache Coreconfigu rations Speed per core DMIPS MHz note 1 Clock rate ARM part number in the main ID register See also editList of ARM processors List of products using ARM processorsNotes edit a b As Dhrystone implied in DMIPS is a synthetic benchmark developed in 1980s it is no longer representative of prevailing workloads use with caution References edit ARM V7 Differences infocenter arm com ARM Information Center Retrieved 1 June 2016 a b ARM processor hardware virtualization support arm com ARM Holdings Retrieved 1 June 2016 a b big LITTLE processing with ARM Cortex A15 amp Cortex A7 PDF arm com ARM Holdings Archived from the original PDF on 17 October 2013 Retrieved 6 August 2014 Cortex A7 processor arm com ARM Holdings Retrieved 1 June 2016 Cortex A8 architecture processors wiki TI com Texas Instruments Archived from the original on 8 August 2014 Retrieved 6 August 2014 The ARM Cortex A9 processors PDF arm com ARM Holdings Archived from the original PDF on 17 November 2014 Retrieved 6 August 2014 a b Cortex A9 processor arm com ARM Holdings Retrieved 15 September 2014 ARM Cortex A17 Cortex A12 processor update Architectures and Processors blog Arm Community blogs Arm Community Cortex A15 processor arm com ARM Holdings Retrieved 9 August 2016 ARM Cortex A17 MPCore processor technical reference manual PDF infocenter arm com ARM Holdings Retrieved 18 September 2014 Klug Brian 7 October 2011 Qualcomm s new Snapdragon S4 MSM8960 amp Krait architecture explored anandtech com Anandtech Retrieved 6 August 2014 Mallia Lou 2007 Qualcomm High Performance Processor Core and Platform for Mobile Applications PDF Archived from the original PDF on 26 April 2017 Retrieved 8 May 2014 Qualcomm s New Snapdragon S4 MSM8960 amp Krait Architecture Explored Qualcomm Snapdragon S4 Krait Performance Preview 1 5 GHZ MSM8960 MDP and Adreno 225 Benchmarks Frumusanu Andrei 22 February 2016 ARM Announces Cortex A32 IoT and Embedded Processor Anandtech com Retrieved 13 June 2016 New Ultra efficient ARM Cortex A32 Processor Expands ARM arm com Retrieved 1 October 2016 Ltd Arm Cortex A34 ARM Developer Retrieved 10 October 2019 Cortex A35 Processor ARM ARM Ltd Frumusanu Andrei ARM Announces New Cortex A35 CPU Ultra High Efficiency For Wearables amp More a b c d e High Performance Processors Other Interesting Talks Phoronix comments Retrieved 24 January 2024 Cortex A53 Processor ARM ARM Ltd a b Processing In Xilinx Devices PDF Digilent documents Retrieved 24 January 2024 a b Matt Humrick 29 May 2017 Exploring DynamIQ and ARM s New CPUs Cortex A75 Cortex A55 Anandtech com Retrieved 29 May 2017 Qualcomm Snapdragon 888 5G Mobile Platform Retrieved 6 January 2021 Based on 18 perf increment over Cortex A53 Arm Cortex A55 Efficient performance from edge to cloud ARM ARM Ltd Smith Andrei Frumusanu Ryan ARM A53 A57 T760 investigated Samsung Galaxy Note 4 Exynos Review anandtech com Retrieved 17 June 2019 a href Template Cite web html title Template Cite web cite web a CS1 maint multiple names authors list link TSMC Delivers First Fully Functional 16FinFET Networking Processor Press release TSMC 25 September 2014 Archived from the original on 20 February 2015 Retrieved 19 February 2015 Cortex A65 Arm Developer ARM Ltd Retrieved 14 July 2020 Cortex A65AE Arm Developer ARM Ltd Retrieved 26 April 2019 Frumusanu Andrei ARM Reveals Cortex A72 Architecture Details Anandtech Retrieved 25 April 2015 a b c ARM s processor lines PDF users nik uni obuda hu November 2018 Retrieved 24 October 2023 Frumusanu Andrei 29 May 2016 The ARM Cortex A73 Artemis Unveiled Anandtech com Retrieved 31 May 2016 Frumusanu Andrei 31 May 2018 ARM Cortex A76 CPU Unveiled Anandtech Retrieved 1 June 2018 Cortex A76AE Arm Developer ARM Ltd Retrieved 14 July 2020 Schor David 26 May 2019 Arm Unveils Cortex A77 Emphasizes Single Thread Performance WikiChip Fuse Retrieved 17 June 2019 According to ARM the Cortex A77 has a 20 IPC single thread performance improvement over its predecessor in Geekbench 4 23 in SPECint2006 35 in SPECfp2006 20 in SPECint2017 and 25 in SPECfp2017 Arm Unveils the Cortex A78 When Less Is More WikiChip Fuse 26 May 2020 Retrieved 28 May 2020 Ltd Arm Cortex A78 ARM Developer Retrieved 28 May 2020 a b c d e Introducing the Arm Cortex X Custom program community arm com Retrieved 28 May 2020 Lal Shimpi Anand 17 September 2013 The iPhone 5s Review The Move to 64 bit AnandTech Retrieved 3 July 2014 a b c d e f g h i Lal Shimpi Anand 31 March 2014 Apple s Cyclone Microarchitecture Detailed AnandTech Retrieved 3 July 2014 Dixon Warren Sinjin 20 January 2014 Samsung 28nm HKMG Inside the Apple A7 Chipworks Archived from the original on 6 April 2014 Retrieved 3 July 2014 Lal Shimpi Anand 17 September 2013 The iPhone 5s Review A7 SoC Explained AnandTech Retrieved 3 July 2014 a b c d e f g h i j Ho Joshua Smith Ryan 2 November 2015 The Apple iPhone 6s and iPhone 6s Plus Review AnandTech Retrieved 13 February 2016 Apple had shifted the microarchitecture in Hurricane A10 from a 6 wide decode from to a 7 wide decode AnandTech 5 October 2018 a b c d Apple A10 Fusion system on a chip specout com Retrieved 1 October 2016 permanent dead link a b c d e Measured and Estimated Cache Sizes AnandTech 5 October 2018 a b Apple A11 New Instruction Set Extensions PDF Apple Inc 8 June 2018 a b Apple A12 Pointer Authentication Codes Jonathan Levin Morpheus 12 September 2018 Archived from the original on 10 October 2018 Retrieved 8 October 2018 a b A13 has ARMv8 4 apparently LLVM project sources thanks Longhorn Jonathan Levin Morpheus 13 March 2020 The Apple A13 SoC Lightning amp Thunder AnandTech 16 October 2019 The A13 s Memory Subsystem Faster L2 More SLC BW AnandTech 16 October 2019 a b c d e f llvm project llvm lib Target AArch64 AArch64 td at main llvm llvm project GitHub github com Retrieved 3 July 2023 Apple Announces The Apple Silicon M1 Ditching x86 What to Expect Based on A14 AnandTech 10 November 2020 Frumusanu Andrei Apple Announces The Apple Silicon M1 Ditching x86 What to Expect Based on A14 anandtech com Retrieved 25 November 2020 Stam Nick 11 August 2014 Mile High Milestone Tegra K1 Denver Will Be First 64 bit ARM Processor for Android NVidia Archived from the original on 12 August 2014 Retrieved 11 August 2014 Gwennap Linley Denver Uses Dynamic Translation to Outperform Mobile Rivals The Linley Group Retrieved 24 April 2015 Ho Joshua 25 August 2016 Hot Chips 2016 NVIDIA Discloses Tegra Parker Details Anandtech Retrieved 25 August 2016 a b De Gelas Johan 16 December 2014 ARM Challenging Intel in the Server Market Anandtech Retrieved 8 March 2017 a b De Gelas Johan 15 June 2016 Investigating the Cavium ThunderX Anandtech Retrieved 8 March 2017 a b 64 bit Cortex Platform To Take on x86 Servers in the Cloud electronic design 5 June 2014 Retrieved 7 February 2015 a b ThunderX CP Family of Workload Optimized Compute Processors PDF Cavium 2014 Retrieved 7 February 2015 A Look at Cavium s New High Performance ARM Microprocessors and the Isambard Supercomputer WikiChip Fuse 3 June 2018 Retrieved 17 June 2019 D30510 Vulcan is now ThunderX2T99 reviews llvm org Kennedy Patrick 7 May 2018 Cavium ThunderX2 256 Thread Arm Platforms Hit General Availability Retrieved 10 May 2018 D21500 AARCH64 Add support for Broadcom Vulcan reviews llvm org Hayes Eric 7 April 2014 IDC HPC USER FORUM PDF hpcuserforum com The Linley Group Processor Conference 2013 linleygroup com ThunderX2 ARM Processors A Game Changing Family of Workload Optimized Processors for Data Center and Cloud Applications Cavium cavium com Broadcom Announces Server Class ARMv8 A Multi Core Processor Architecture Broadcom 15 October 2013 Retrieved 11 August 2014 a b c Kennedy Patrick 9 May 2018 Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option Serve the Home Retrieved 10 May 2018 a b c d Frumusanu Andrei 16 March 2020 Marvell Announces ThunderX3 96 Cores amp 384 Thread 3rd Gen Arm Server Processor Ganesh T S 3 October 2014 ARMv8 Goes Embedded with Applied Micro s HeliX SoCs AnandTech Retrieved 9 October 2014 Morgan Timothy Prickett 12 August 2014 Applied Micro Plots Out X Gene ARM Server Future Enterprisetech Retrieved 9 October 2014 a b De Gelas Johan 15 March 2017 AppliedMicro s X Gene 3 SoC Begins Sampling Anandtech Retrieved 15 March 2017 Snapdragon 820 and Kryo CPU heterogeneous computing and the role of custom compute Qualcomm 2 September 2015 Retrieved 6 September 2015 Frumusanu Ryan Smith Andrei The Qualcomm Snapdragon 820 Performance Preview Meet Kryo a href Template Cite web html title Template Cite web cite web a CS1 maint multiple names authors list link a b c Smith Andrei Frumusanu Ryan The Snapdragon 845 Performance Preview Setting the Stage for Flagship Android 2018 Retrieved 11 June 2018 a href Template Cite news html title Template Cite news cite news a CS1 maint multiple names authors list link Shilov Anton 16 December 2016 Qualcomm Demos 48 Core Centriq 2400 SoC in Action Begins Sampling Anandtech Retrieved 8 March 2017 In 2015 Qualcomm teamed up with Xilinx and Mellanox to ensure that its server SoCs are compatible with FPGA based accelerators and data center connectivity solutions the fruits of this partnership will likely emerge in 2018 at best a b c d Cutress Ian 20 August 2017 Analyzing Falkor s Microarchitecture Anandtech Retrieved 21 August 2017 The CPU cores code named Falkor will be ARMv8 0 compliant although with ARMv8 1 features allowing software to potentially seamlessly transition from other ARM environments or need a recompile The Centriq 2400 family is set to be AArch64 only without support for AArch32 Qualcomm states that this saves some power and die area but that they primarily chose this route because the ecosystems they are targeting have already migrated to 64 bit Qualcomm s Chris Bergen Senior Director of Product Management for the Centriq 2400 stated that the majority of new and upcoming companies have started off with 64 bit as their base in the data center and not even considering 32 bit which is a reason for the AArch64 only choice here Micro op cache L0 I cache with Way prediction The L1 I cache is 64KB which is similar to other ARM architecture core designs and also uses 64 byte lines but with an 8 way associativity To software as the L0 is transparent the L1 I cache will show as an 88KB cache Shrout Ryan 8 November 2017 Qualcomm Centriq 2400 Arm based Server Processor Begins Commercial Shipment PC Per Retrieved 8 November 2017 a b Ho Joshua Hot Chips 2016 Exynos M1 Architecture Disclosed a b Frumusanu Andrei Samsung Announces Exynos 8890 with Cat 12 13 Modem and Custom CPU a b Frumusanu Andrei 23 January 2018 The Samsung Exynos M3 6 wide Decode with 50 IPC Increase Anandtech Retrieved 25 January 2018 Frumusanu Andrei Hot Chips 2016 Exynos M1 Architecture Disclosed Anandtech Retrieved 29 May 2017 Neural network spotted deep inside Samsung s Galaxy S7 silicon brain The Register Frumusanu Andrei Hot Chips 2018 Samsung s Exynos M3 CPU Architecture Deep Dive anandtech com Retrieved 17 June 2019 Schor David 14 January 2019 Samsung Discloses Exynos M4 Changes Upgrades Support for ARMv8 2 Rearranges The Back End WikiChip Fuse Retrieved 17 June 2019 Frumusanu Andrei ISCA 2020 Evolution of the Samsung Exynos CPU Microarchitecture anandtech com Retrieved 24 January 2021 Fujitsu High Performance CPU for the Post K Computer PDF 21 July 2018 retrieved 16 September 2019 Arm A64fx and Post K Game Changing CPU amp Supercomputer for HPC and its Convergence of with Big Data AI PDF 3 April 2019 retrieved 16 September 2019 Fujitsu Successfully Triples the Power Output of Gallium Nitride Transistors Fujitsu Global fujitsu com Retrieved 23 November 2020 Schor David 3 May 2019 Huawei Expands Kunpeng Server CPUs Plans SMT SVE For Next Gen WikiChip Fuse Retrieved 13 December 2019 Retrieved from https en wikipedia org w index php title Comparison of ARM processors amp oldid 1198506569 ARMv7 A, wikipedia, wiki, book, books, library,

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