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Wikipedia

MIX (abstract machine)

MIX is a hypothetical computer used in Donald Knuth's monograph, The Art of Computer Programming (TAOCP). MIX's model number is 1009, which was derived by combining the model numbers and names of several contemporaneous, commercial machines deemed significant by the author. Also, "MIX" read as a Roman numeral is 1009.

MIX
DesignerDonald Knuth
Bits31-bit
Introduced1968
Designaccumulator machine
Typehypothetical
EncodingFixed
BranchingCondition code and register test
EndiannessBig
OpenYes, and royalty free
Registers
9 in total

The 1960s-era MIX has since been superseded by a new (also hypothetical) computer architecture, MMIX, to be incorporated in forthcoming editions of TAOCP.

Software implementations for both the MIX and MMIX architectures have been developed by Knuth and made freely available (named "MIXware" and "MMIXware", respectively). Several derivatives of Knuth's MIX/MMIX emulators also exist. GNU MDK is one such software package; it is free and runs on a wide variety of platforms.

Their purpose for education is quite similar to John L. Hennessy's and David A. Patterson's DLX architecture, from Computer Organization and Design - The Hardware Software Interface.

Architecture edit

MIX is a hybrid binarydecimal computer. When programmed in binary, each byte has 6 bits (values range from 0 to 63). In decimal, each byte has 2 decimal digits (values range from 0 to 99). Bytes are grouped into words of five bytes plus a sign. Most programs written for MIX will work in either binary or decimal, so long as they do not try to store a value greater than 63 in a single byte.

A word has the range −1,073,741,823 to 1,073,741,823 (inclusive) in binary mode, and −9,999,999,999 to 9,999,999,999 (inclusive) in decimal mode. The sign-and-magnitude representation of integers in the MIX architecture distinguishes between “−0” and “+0.” This contrasts with modern computers, whose two's-complement representation of integer quantities includes a single representation for zero, but whose range for a given number of bits includes one more negative integer than the number of representable positive integers.

MIX registers
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Registers
± A1 A2 A3 A4 A5 rA, Accumulator
± X1 X2 X3 X4 X5 rX, Extension
Index registers
  ± I1.4 I1.5 rI1, Index 1
  ± I2.4 I2.5 rI2, Index 2
  ± I3.4 I3.5 rI3, Index 3
  ± I4.4 I4.5 rI4, Index 4
  ± I5.4 I5.5 rI5, Index 5
  ± I6.4 I6.5 rI6, Index 6
Program counter
  J4 J5 rJ, Jump
Condition code flags
  O Overflow flag
  <=> Comparison flag

Registers edit

There are 9 registers in MIX:

  • rA: Accumulator (full word, five bytes and a sign).
  • rX: Extension (full word, five bytes and a sign).
  • rI1, rI2, rI3, rI4, rI5, rI6: Index registers (two bytes and a sign).
  • rJ: Jump address (two bytes, always positive).

A byte is assumed to be at least 6 bits. Most instructions can specify which of the "fields" (bytes) of a register are to be altered, using a suffix of the form (first:last). The zeroth field is the one-bit sign.

MIX also records whether the previous operation overflowed, and has a one-trit comparison indicator (less than, equal to, or greater than).

Memory and input/output edit

The MIX machine has 4000 words of storage (each with 5 bytes and a sign), addressed from 0 to 3999. A variety of input and output devices are also included:

  • Tape units (devices 0...7).
  • Disk or drum units (devices 8...15).
  • Card reader (device 16).
  • Card punch (device 17).
  • Line printer (device 18).
  • Typewriter terminal (device 19).
  • Paper tape (device 20).

Instructions edit

Each machine instruction in memory occupies one word, and consists of 4 parts: the address (2 bytes and the sign of the word) in memory to read or write; an index specification (1 byte, describing which rI index register to use) to add to the address; a modification (1 byte) that specifies which parts of the register or memory location will be read or altered; and the operation code (1 byte). All operation codes have an associated mnemonic.

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
± Address Index Modification Operation

MIX programs frequently use self-modifying code, in particular to return from a subroutine, as MIX lacks an automatic subroutine return stack. Self-modifying code is facilitated by the modification byte, allowing the program to store data to, for example, the address part of the target instruction, leaving the rest of the instruction unmodified.

MIX programs are typically constructed using the MIXAL assembly language; for an example, see the list hello world programs page.

LDA ADDR,i(0:5) rA := memory[ADDR + rIi];
LDX ADDR,i(0:5) rX := memory[ADDR + rIi];
LD? ADDR,i(0:5) rI? := memory[ADDR + rIi];
LDAN ADDR,i(0:5) rA := - memory[ADDR + rIi];
LDXN ADDR,i(0:5) rX := - memory[ADDR + rIi];
LD?N ADDR,i(0:5) rI? := - memory[ADDR + rIi];
STA ADDR,i(0:5) memory[ADDR + rIi] := rA;
STX ADDR,i(0:5) memory[ADDR + rIi] := rX;
ST? ADDR,i(0:5) memory[ADDR + rIi] := rI?;
STJ ADDR,i(0:5) memory[ADDR + rIi] := rJ;
STZ ADDR,i(0:5) memory[ADDR + rIi] := 0;
ADD ADDR,i(0:5) rA := rA + memory[ADDR + rIi];
SUB ADDR,i(0:5) rA := rA - memory[ADDR + rIi];
MUL ADDR,i(0:5) (rA,rX) := rA * memory[ADDR + rIi];
DIV ADDR,i(0:5)
rA := int( (rA,rX) / memory[ADDR + rIi] ); rX := (rA,rX) % memory[ADDR + rIi]; 
ENTA ADDR,i rA := ADDR + rIi;
ENTX ADDR,i rX := ADDR + rIi;
ENT? ADDR,i rI? := ADDR + rIi;
ENNA ADDR,i rA := - ADDR - rIi;
ENNX ADDR,i rX := - ADDR - rIi;
ENN? ADDR,i rI? := - ADDR - rIi;
INCA ADDR,i rA := rA + ADDR + rIi;
INCX ADDR,i rX := rX + ADDR + rIi;
INC? ADDR,i rI? := rI? + ADDR + rIi;
DECA ADDR,i rA := rA - ADDR - rIi;
DECX ADDR,i rX := rX - ADDR - rIi;
DEC? ADDR,i rI? := rI? - ADDR - rIi;
CMPA ADDR,i(0:5) compare rA with memory[ADDR + rIi] and set comparison flag;
CMPX ADDR,i(0:5) compare rX with memory[ADDR + rIi] and set comparison flag;
CMP? ADDR,i(0:5) compare rI? with memory[ADDR + rIi] and set comparison flag;
JMP ADDR,i
rJ := address of next instruction; goto ADDR + rIi; 
JSJ ADDR,i goto ADDR + rIi;
JOV ADDR,i
if (overflow) then  overflow := false;   goto ADDR + rIi; 
JNOV ADDR,i
if (no overflow) then  goto ADDR + rIi; else   overflow := false; 
JL, JE, JG ADDR,i
JGE, JNE, JLE ADDR,i
if (less, equal, greater) then goto ADDR + rIi; if (no less, unequal, no greater) then goto ADDR + rIi; 
JAN/JAZ/JAP ADDR,i
JANN/JANZ/JANP ADDR,i
if (rA<0 or rA==0 or rA>0) then goto ADDR + rIi; if (rA>=0 or rA!=0 or rA<=0) then goto ADDR + rIi; 
JXN/JXZ/JXP ADDR,i
JXNN/JXNZ/JXNP ADDR,i
if (rX<0 or rX==0 or rX>0) then goto ADDR + rIi; if (rX>=0 or rX!=0 or rX<=0) then goto ADDR + rIi; 
J?N/J?Z/J?P ADDR,i
J?NN/J?NZ/J?NP ADDR,i
if (rI?<0 or rI?==0 or rI?>0) then goto ADDR + rIi; if (rI?>=0 or rI?!=0 or rI?<=0) then goto ADDR + rIi;
MOVE ADDR,i(F)
for (n = 0; n < F; n++, rI1++)  memory[rI1] := memory[ADDR+rIi+n]; 
SLA/SRA ADDR,i
SLAX/SRAX ADDR,i
SLC/SRC ADDR,i
shift rA to the left/right by ADDR+rIi bytes
shift (rA,rX) to the left/right by ADDR+rIi bytes
rotate (rA,rX) to the left/right by ADDR+rIi bytes
NOP do nothing;
HLT halt execution;
IN ADDR,i(F) read in one block from input unit F
into memory[ADDR + rIi] onwards;
OUT ADDR,i(F) output one block to unit F
from memory[ADDR + rIi] onwards;
IOC ADDR,i(F) send control instruction to i/o unit F;
JRED ADDR,i(F) if (i/o unit F is ready) then goto ADDR + rIi;
JBUS ADDR,i(F) if (i/o unit F is busy) then goto ADDR + rIi;
NUM rA := numerical value of characters in (rA,rX);
CHAR (rA,rX) := character codes representing value of rA;

Implementations edit

MIX has been implemented in software by:

  • Knuth's MIXWare and the derived GNU MDK;
  • 9front's mix(1);[1] and
  • Hardware::Simulator::MIX on CPAN.[2]

An implementation of MIX was created for the iCE40HX8K FPGA board in 2021.[3]

See also edit

References edit

  1. ^ mix(1) – 9front manual page
  2. ^ Hardware::Simulator::MIX Perl module from CPAN
  3. ^ "Michael Schröder / mix-fgpa". GitLab.

External links edit

  • MMIX 2009: A RISC Computer for the Third Millennium Knuth's official MIX page
  • MMIX News Knuth's official MIX news
  • MIX: the design of a typical computer and its assembly language on Open Library at the Internet Archive, Knuth's original 1970 official MIX book, with Tom Mix on the cover.
  • MMIXware: A RISC Computer for the Third Millennium Knuth's official MIX book
  • MIX-MMIX/MIXAL-MMIXAL at Curlie

abstract, machine, this, article, needs, additional, citations, verification, please, help, improve, this, article, adding, citations, reliable, sources, unsourced, material, challenged, removed, find, sources, abstract, machine, news, newspapers, books, schol. This article needs additional citations for verification Please help improve this article by adding citations to reliable sources Unsourced material may be challenged and removed Find sources MIX abstract machine news newspapers books scholar JSTOR August 2012 Learn how and when to remove this template message MIX is a hypothetical computer used in Donald Knuth s monograph The Art of Computer Programming TAOCP MIX s model number is 1009 which was derived by combining the model numbers and names of several contemporaneous commercial machines deemed significant by the author Also MIX read as a Roman numeral is 1009 MIXDesignerDonald KnuthBits31 bitIntroduced1968Designaccumulator machineTypehypotheticalEncodingFixedBranchingCondition code and register testEndiannessBigOpenYes and royalty freeRegisters9 in totalThe 1960s era MIX has since been superseded by a new also hypothetical computer architecture MMIX to be incorporated in forthcoming editions of TAOCP Software implementations for both the MIX and MMIX architectures have been developed by Knuth and made freely available named MIXware and MMIXware respectively Several derivatives of Knuth s MIX MMIX emulators also exist GNU MDK is one such software package it is free and runs on a wide variety of platforms Their purpose for education is quite similar to John L Hennessy s and David A Patterson s DLX architecture from Computer Organization and Design The Hardware Software Interface Contents 1 Architecture 1 1 Registers 1 2 Memory and input output 1 3 Instructions 2 Implementations 3 See also 4 References 5 External linksArchitecture editMIX is a hybrid binary decimal computer When programmed in binary each byte has 6 bits values range from 0 to 63 In decimal each byte has 2 decimal digits values range from 0 to 99 Bytes are grouped into words of five bytes plus a sign Most programs written for MIX will work in either binary or decimal so long as they do not try to store a value greater than 63 in a single byte A word has the range 1 073 741 823 to 1 073 741 823 inclusive in binary mode and 9 999 999 999 to 9 999 999 999 inclusive in decimal mode The sign and magnitude representation of integers in the MIX architecture distinguishes between 0 and 0 This contrasts with modern computers whose two s complement representation of integer quantities includes a single representation for zero but whose range for a given number of bits includes one more negative integer than the number of representable positive integers MIX registers30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 bit position Registers A1 A2 A3 A4 A5 rA Accumulator X1 X2 X3 X4 X5 rX ExtensionIndex registers I1 4 I1 5 rI1 Index 1 I2 4 I2 5 rI2 Index 2 I3 4 I3 5 rI3 Index 3 I4 4 I4 5 rI4 Index 4 I5 4 I5 5 rI5 Index 5 I6 4 I6 5 rI6 Index 6Program counter J4 J5 rJ JumpCondition code flags O Overflow flag lt gt Comparison flagRegisters edit There are 9 registers in MIX rA Accumulator full word five bytes and a sign rX Extension full word five bytes and a sign rI1 rI2 rI3 rI4 rI5 rI6 Index registers two bytes and a sign rJ Jump address two bytes always positive A byte is assumed to be at least 6 bits Most instructions can specify which of the fields bytes of a register are to be altered using a suffix of the form first last The zeroth field is the one bit sign MIX also records whether the previous operation overflowed and has a one trit comparison indicator less than equal to or greater than Memory and input output edit The MIX machine has 4000 words of storage each with 5 bytes and a sign addressed from 0 to 3999 A variety of input and output devices are also included Tape units devices 0 7 Disk or drum units devices 8 15 Card reader device 16 Card punch device 17 Line printer device 18 Typewriter terminal device 19 Paper tape device 20 Instructions edit Each machine instruction in memory occupies one word and consists of 4 parts the address 2 bytes and the sign of the word in memory to read or write an index specification 1 byte describing which rI index register to use to add to the address a modification 1 byte that specifies which parts of the register or memory location will be read or altered and the operation code 1 byte All operation codes have an associated mnemonic 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Address Index Modification OperationMIX programs frequently use self modifying code in particular to return from a subroutine as MIX lacks an automatic subroutine return stack Self modifying code is facilitated by the modification byte allowing the program to store data to for example the address part of the target instruction leaving the rest of the instruction unmodified MIX programs are typically constructed using the MIXAL assembly language for an example see the list hello world programs page span class nf LDA span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n rA span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span span class nf LDX span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n rX span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span LD ADDR i 0 5 rI memory ADDR rIi span class nf LDAN span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n rA span span class w span span class o span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span span class nf LDXN span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n rX span span class w span span class o span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span LD N ADDR i 0 5 rI memory ADDR rIi span class nf STA span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class w span span class o span span class w span span class n rA span span class o span span class nf STX span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class w span span class o span span class w span span class n rX span span class o span ST ADDR i 0 5 memory ADDR rIi rI span class nf STJ span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class w span span class o span span class w span span class n rJ span span class o span span class nf STZ span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class w span span class o span span class w span span class mi 0 span span class o span span class nf ADD span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n rA span span class w span span class o span span class w span span class n rA span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span span class nf SUB span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class n rA span span class w span span class o span span class w span span class n rA span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span span class nf MUL span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span span class p span span class n rA span span class o span span class n rX span span class p span span class w span span class o span span class w span span class n rA span span class w span span class o span span class w span span class n memory span span class p span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class p span span class o span span class nf DIV span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span rA int rA rX memory ADDR rIi rX rA rX memory ADDR rIi span class nf ENTA span span class w span span class no ADDR span span class p span span class no i span span class n rA span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span span class nf ENTX span span class w span span class no ADDR span span class p span span class no i span span class n rX span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span ENT ADDR i rI ADDR rIi span class nf ENNA span span class w span span class no ADDR span span class p span span class no i span span class n rA span span class w span span class o span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span span class nf ENNX span span class w span span class no ADDR span span class p span span class no i span span class n rX span span class w span span class o span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span ENN ADDR i rI ADDR rIi span class nf INCA span span class w span span class no ADDR span span class p span span class no i span span class n rA span span class w span span class o span span class w span span class n rA span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span span class nf INCX span span class w span span class no ADDR span span class p span span class no i span span class n rX span span class w span span class o span span class w span span class n rX span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span INC ADDR i rI rI ADDR rIi span class nf DECA span span class w span span class no ADDR span span class p span span class no i span span class n rA span span class w span span class o span span class w span span class n rA span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span span class nf DECX span span class w span span class no ADDR span span class p span span class no i span span class n rX span span class w span span class o span span class w span span class n rX span span class w span span class o span span class w span span class nb ADDR span span class w span span class o span span class w span span class n rIi span span class o span DEC ADDR i rI rI ADDR rIi span class nf CMPA span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span compare rA with memory ADDR rIi and set comparison flag span class nf CMPX span span class w span span class no ADDR span span class p span span class no i span span class p span span class mi 0 span span class p span span class mi 5 span span class p span compare rX with memory ADDR rIi and set comparison flag CMP ADDR i 0 5 compare rI with memory ADDR rIi and set comparison flag span class nf JMP span span class w span span class no ADDR span span class p span span class no i span rJ address of next instruction goto ADDR rIi span class nf JSJ span span class w span span class no ADDR span span class p span span class no i span span class k goto span span class w span span class nl ADDR span span class w span span class o span span class w span span class nl rIi span span class o span span class nf JOV span span class w span span class no ADDR span span class p span span class no i span if overflow then overflow false goto ADDR rIi span class nf JNOV span span class w span span class no ADDR span span class p span span class no i span if no overflow then goto ADDR rIi else overflow false JL JE JG ADDR iJGE JNE JLE ADDR i if less equal greater then goto ADDR rIi if no less unequal no greater then goto ADDR rIi JAN JAZ JAP ADDR iJANN JANZ JANP ADDR i if rA lt 0 or rA 0 or rA gt 0 then goto ADDR rIi if rA gt 0 or rA 0 or rA lt 0 then goto ADDR rIi JXN JXZ JXP ADDR iJXNN JXNZ JXNP ADDR i if rX lt 0 or rX 0 or rX gt 0 then goto ADDR rIi if rX gt 0 or rX 0 or rX lt 0 then goto ADDR rIi J N J Z J P ADDR iJ NN J NZ J NP ADDR i if rI lt 0 or rI 0 or rI gt 0 then goto ADDR rIi if rI gt 0 or rI 0 or rI lt 0 then goto ADDR rIi span class nf MOVE span span class w span span class no ADDR span span class p span span class no i span span class p span span class no F span span class p span for n 0 n lt F n rI1 memory rI1 memory ADDR rIi n SLA SRA ADDR iSLAX SRAX ADDR iSLC SRC ADDR i shift rA to the left right by ADDR rIi bytesshift rA rX to the left right by ADDR rIi bytesrotate rA rX to the left right by ADDR rIi bytesNOP do nothing HLT halt execution span class nf IN span span class w span span class no ADDR span span class p span span class no i span span class p span span class no F span span class p span read in one block from input unit Finto memory ADDR rIi onwards span class nf OUT span span class w span span class no ADDR span span class p span span class no i span span class p span span class no F span span class p span output one block to unit Ffrom memory ADDR rIi onwards span class nf IOC span span class w span span class no ADDR span span class p span span class no i span span class p span span class no F span span class p span send control instruction to i o unit F span class nf JRED span span class w span span class no ADDR span span class p span span class no i span span class p span span class no F span span class p span span class k if span span class w span span class p span span class n i span span class o span span class n o span span class w span span class k unit span span class w span span class n F span span class w span span class k is span span class w span span class n ready span span class p span span class w span span class k then span span class w span span class k goto span span class w span span class nl ADDR span span class w span span class o span span class w span span class nl rIi span span class o span span class nf JBUS span span class w span span class no ADDR span span class p span span class no i span span class p span span class no F span span class p span span class k if span span class w span span class p span span class n i span span class o span span class n o span span class w span span class k unit span span class w span span class n F span span class w span span class k is span span class w span span class n busy span span class p span span class w span span class k then span span class w span span class k goto span span class w span span class nl ADDR span span class w span span class o span span class w span span class nl rIi span span class o span NUM rA numerical value of characters in rA rX CHAR rA rX character codes representing value of rA Implementations editMIX has been implemented in software by Knuth s MIXWare and the derived GNU MDK 9front s mix 1 1 and Hardware Simulator MIX on CPAN 2 An implementation of MIX was created for the iCE40HX8K FPGA board in 2021 3 See also editEducational programming language DLX LC 3 Little man computer MMIX MikroSimReferences edit mix 1 9front manual page Hardware Simulator MIX Perl module from CPAN Michael Schroder mix fgpa GitLab External links editMMIX 2009 A RISC Computer for the Third Millennium Knuth s official MIX page MMIX News Knuth s official MIX news MIX the design of a typical computer and its assembly language on Open Library at the Internet Archive Knuth s original 1970 official MIX book with Tom Mix on the cover MMIXware A RISC Computer for the Third Millennium Knuth s official MIX book MIX MMIX MIXAL MMIXAL at Curlie Retrieved from https en wikipedia org w index php title MIX abstract machine amp oldid 1194482434, wikipedia, wiki, book, books, library,

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