MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer instruction set architecture (ISA), including both required and optional components, as described by the military standard document MIL-STD-1750A (1980). Since August 1996, it has been inactive for new designs.
In addition to the core ISA, the definition defines optional instructions, such as a FPU and MMU. Importantly, the standard does not define the implementation details of a 1750A processor.
Bound copy, from the 1980s, of the MIL-STD-1750A specification document
The 1750A supports 216 16-bit words of memory for the core standard. The standard defines an optional memory management unit that allows 220 16-bit words of memory using 512 page mapping registers (in the I/O space), defining separate instruction and data spaces, and keyed memory access control.
Most instructions are 16 bits, although some have a 16-bit extension. The standard computer has 16 general purpose 16-bit registers (0 through 15). Registers 1 through 15 can be used as index registers. Registers 12 through 15 can be used as base registers.
Any of the 16 registers can be used as a stackpointer for the SJS and URS instructions (stack jump subroutine and unstack return subroutine), but only register 15 is used as the stack pointer for the PSHM and POPM instructions (push multiple and pop multiple).
The computer has instructions for 16, and 32-bit binary arithmetic, as well as 32 and 48 bit floating point. I/O is generally via the I/O instructions (XIO and VIO), which have a separate 216 16-bit word address space and may have a specialized bus.
Implementations
Performance Semiconductor P1750AE
Because MIL-STD-1750A does not define implementation details, 1750A products are available from a wide variety of companies in the form of component, board, and system-level offerings implemented in myriad technologies, often the most advanced and exotic of their respective periods (e.g. GaAs, ECL, SoS).
1750A systems often offer high levels of protection from radiation and other hazardous environments, making them particularly suited for military, aviation and space applications.
Examples of MIL-STD-1750A implementations include:
CPU Technology, Inc. CPU1750A-FB, a high performance 1750A SOC designed to give existing applications a late life performance boost.
GEC-Plessey RH1750, a radiation-hardened version for aerospace and space flight applications. GEC-Plessey, under its previous iteration as Marconi Electronic Devices, also initially developed the MAS281 and MA31750A[1] series of processors, later made available through Dynex Semiconductor
Honeywell HX1750, fabricated on Honeywell's Silicon on Insulator CMOS (SOI-IV) process giving radiation hardness. The HX1750 includes an FPU and peripherals on chip.
Johns Hopkins University Applied Physics Laboratory (JHU/APL) MIL-STD-1750AAV space flight qualified processor. A multi-board silicon on sapphire implementation specifically designed for space flight.
National Semiconductor PACE P1750A. The PACE normally runs a version of the Data General Nova instruction set, but was adapted to run MIL-STD-1750A using new microcode. The family includes the P1750A CPU, the P1750AE Enhanced CPU, the P1753 Memory Management Unit (MMU), the P1754 Processor Interface Chip (PIC) and the P1757ME Multi-Chip Module. This line was passed to Performance Semiconductor and then Pyramid Semiconductor in 2003.
There are also C compilers, for example Cleanscape XTC-1750A. Older versions of GNUGCC contain support for MIL-STD-1750A; it was declared obsolete in version 3.1, and removed in subsequent versions.
In addition, DDC-I provides its SCORE Integrated Development Environment (IDE) with both Ada95 and C compilers, and TADS (Tartan Ada Development System) Ada83 development environment, both targeting processors based on MIL-STD-1750A.
Deployments
The U.S. Air Force defined the standard in order to have a common computing architecture and thereby reduce the costs of software and computer systems for all military computing needs. This includes embedded tasks such as aircraft and missile control systems as well as more mundane general military computing needs.
The advantages of this concept are recognized outside of the USAF, and the 1750A has been adopted by other organizations such as the European Space Agency, NASA, Israeli Aircraft Industries, and many projects in academia.
Examples of military aircraft using the 1750A include:
Fully space-rated implementations make the 1750A one of the few types of computers that are applicable for use in deep space applications. Example spacecraft that use the 1750A are:
ESA Envisat - Envisat's ASAR instrument, built by Matra Marconi Space and comprising the Central Electronics Sub-Assembly and Antenna Sub-Assembly used a total of 42 GEC-Plessey MA31750A processors in a dual-redundant configuration
The MIL-STD-1750B was to be a successor architecture to the MIL-STD-1750A, with added and expanded features, some of which were optional. By the mid-1980s there was a published draft of the 1750B available,[8] and some vendors began implementations for it. However, no finalized specification was ever issued for the 1750B, as military and industry attention shifted to 32-bit architectural alternatives such as the MIPS R3000.
References
^"mas31750 DataSheet - PDF - www.BestDatasheets.com". bestdatasheets.com.
^. dtic.mil. Archived from the original on 2011-08-23. Retrieved 2010-06-10.
^"Onboard processor validation for space applications - IEEE Conference Publication". doi:10.1109/ICACCI.2015.7275677. S2CID 16385798. {{cite journal}}: Cite journal requires |journal= (help)
^(PDF). Archived from the original (PDF) on 2014-09-01. Retrieved 2014-09-23.{{cite web}}: CS1 maint: archived copy as title (link)
^S. Lloyd Plehaty, "Software Considerations for Interfacing Avionics Computers and Mux Buses", SAE Transactions Vol. 95, Section 7: Aerospace (1986), pp. 63–68.
External links
DOD MIL-STD-1750 standard
DOD MIL-STD-1750 standard(PDF), with updated Notice 1, 21 May 1982
DOD MIL-STD-1750 standard(HTML), with updated Notice 1, 21 May 1982
Software Vendor Information
Specification and vendor information
Ada83 compiler for the 1750A processor
IDE, Ada95, EC++ and ANSI C compilers for the 1750A processor
Ada and ANSI C compilers
References to use in spacecraft
Pyramid Semiconductor P1750A-SOS Processor
December 29, 2022
1750a, 1750a, formal, definition, computer, instruction, architecture, including, both, required, optional, components, described, military, standard, document, 1980, since, august, 1996, been, inactive, designs, 1750abits16, bitintroduced1980designcmos, gaas,. MIL STD 1750A or 1750A is the formal definition of a 16 bit computer instruction set architecture ISA including both required and optional components as described by the military standard document MIL STD 1750A 1980 Since August 1996 it has been inactive for new designs 1750ABits16 bitIntroduced1980DesignCMOS GaAs ECL SoSTypeCISC citation needed Encoding16 bit instructionsExtensionsFPU MMURegistersGeneral purpose16 16 bitFloating pointOptional in specificationIn addition to the core ISA the definition defines optional instructions such as a FPU and MMU Importantly the standard does not define the implementation details of a 1750A processor Contents 1 Internals 2 Implementations 3 Programming 4 Deployments 4 1 Use in space 5 1750B 6 References 7 External linksInternals Edit Bound copy from the 1980s of the MIL STD 1750A specification document The 1750A supports 216 16 bit words of memory for the core standard The standard defines an optional memory management unit that allows 220 16 bit words of memory using 512 page mapping registers in the I O space defining separate instruction and data spaces and keyed memory access control Most instructions are 16 bits although some have a 16 bit extension The standard computer has 16 general purpose 16 bit registers 0 through 15 Registers 1 through 15 can be used as index registers Registers 12 through 15 can be used as base registers Any of the 16 registers can be used as a stack pointer for the SJS and URS instructions stack jump subroutine and unstack return subroutine but only register 15 is used as the stack pointer for the PSHM and POPM instructions push multiple and pop multiple The computer has instructions for 16 and 32 bit binary arithmetic as well as 32 and 48 bit floating point I O is generally via the I O instructions XIO and VIO which have a separate 216 16 bit word address space and may have a specialized bus Implementations Edit Performance Semiconductor P1750AE Because MIL STD 1750A does not define implementation details 1750A products are available from a wide variety of companies in the form of component board and system level offerings implemented in myriad technologies often the most advanced and exotic of their respective periods e g GaAs ECL SoS 1750A systems often offer high levels of protection from radiation and other hazardous environments making them particularly suited for military aviation and space applications Examples of MIL STD 1750A implementations include CPU Technology Inc CPU1750A FB a high performance 1750A SOC designed to give existing applications a late life performance boost Delco Systems Operations Magic V 1750 Processor Dynex Semiconductor MAS281 A radiation hardened SOC implementation on a 64 pin multichip module with an optional MMU GEC Plessey RH1750 a radiation hardened version for aerospace and space flight applications GEC Plessey under its previous iteration as Marconi Electronic Devices also initially developed the MAS281 and MA31750A 1 series of processors later made available through Dynex Semiconductor Honeywell HX1750 fabricated on Honeywell s Silicon on Insulator CMOS SOI IV process giving radiation hardness The HX1750 includes an FPU and peripherals on chip Johns Hopkins University Applied Physics Laboratory JHU APL MIL STD 1750AAV space flight qualified processor A multi board silicon on sapphire implementation specifically designed for space flight Marconi Electronic Devices MIL STD 1750A McDonnell Douglas MD 281 A radiation hardened SoS three die implementation on a 64 pin multichip module Fairchild Semiconductor F9450 series National Semiconductor PACE P1750A The PACE normally runs a version of the Data General Nova instruction set but was adapted to run MIL STD 1750A using new microcode The family includes the P1750A CPU the P1750AE Enhanced CPU the P1753 Memory Management Unit MMU the P1754 Processor Interface Chip PIC and the P1757ME Multi Chip Module This line was passed to Performance Semiconductor and then Pyramid Semiconductor in 2003 Royal Aircraft Establishment Farnborough MIL STD 1750A implementation in AMD 2901 bit slice technology 2 Programming Edit Software vendor from the 1980s offering cross compilers from three language languages to the 1750A Processors based on MIL STD 1750A are often programmed in JOVIAL a high level programming language defined by the United States Department of Defense which is derived from ALGOL 58 Later the Ada was heavily used There are also C compilers for example Cleanscape XTC 1750A Older versions of GNU GCC contain support for MIL STD 1750A it was declared obsolete in version 3 1 and removed in subsequent versions In addition DDC I provides its SCORE Integrated Development Environment IDE with both Ada95 and C compilers and TADS Tartan Ada Development System Ada83 development environment both targeting processors based on MIL STD 1750A Deployments EditThe U S Air Force defined the standard in order to have a common computing architecture and thereby reduce the costs of software and computer systems for all military computing needs This includes embedded tasks such as aircraft and missile control systems as well as more mundane general military computing needs The advantages of this concept are recognized outside of the USAF and the 1750A has been adopted by other organizations such as the European Space Agency NASA Israeli Aircraft Industries and many projects in academia Examples of military aircraft using the 1750A include IAI Lavi fighter IBM Federal Systems AP 102 Avionics Computer used in various roles including the USAF F 111 avionics upgrade US Army AH 64D Apache Longbow Helicopter USAF F 16 Digital Flight Control System and Fire Control Computer USN F 18 RFCS Flight Control ComputerUse in space Edit Fully space rated implementations make the 1750A one of the few types of computers that are applicable for use in deep space applications Example spacecraft that use the 1750A are EOS Aqua Aura and Terra ESA Cluster ESA Envisat Envisat s ASAR instrument built by Matra Marconi Space and comprising the Central Electronics Sub Assembly and Antenna Sub Assembly used a total of 42 GEC Plessey MA31750A processors in a dual redundant configuration ESA Rosetta ISRO GSAT INSAT IRS series of spacecraft 3 ISRO Mars Orbiter Mission 4 ISRO Space Recovery Experiment 1 Guidance and Navigation Computer 5 Midcourse Space Experiment MSX spacecraft developed at JHU APL MSTI 1 2 and 3 NASA Cassini NASA Landsat 7 NASA Mars Global Surveyor Naval Research Laboratory Clementine Lunar Orbiter NOAA GOES 13 GOES O and GOES P Orbital Sciences Corporation commercial communication satellite platforms 6 7 USAF Titan 4 Guidance Computer1750B EditThe MIL STD 1750B was to be a successor architecture to the MIL STD 1750A with added and expanded features some of which were optional By the mid 1980s there was a published draft of the 1750B available 8 and some vendors began implementations for it However no finalized specification was ever issued for the 1750B as military and industry attention shifted to 32 bit architectural alternatives such as the MIPS R3000 References Edit mas31750 DataSheet PDF www BestDatasheets com bestdatasheets com An Implementation of MIL STD 1750 Airborne Computer Instruction Set Architecture dtic mil Archived from the original on 2011 08 23 Retrieved 2010 06 10 Onboard processor validation for space applications IEEE Conference Publication doi 10 1109 ICACCI 2015 7275677 S2CID 16385798 a href Template Cite journal html title Template Cite journal cite journal a Cite journal requires journal help Archived copy PDF Archived from the original PDF on 2014 09 01 Retrieved 2014 09 23 a href Template Cite web html title Template Cite web cite web a CS1 maint archived copy as title link ftp ftp elet polimi it users Marco Lovera ESAGNC08 S08 07 Veeraraghavan pdf permanent dead link Orbital ATK PDF orbital com Orbital ATK PDF orbital com S Lloyd Plehaty Software Considerations for Interfacing Avionics Computers and Mux Buses SAE Transactions Vol 95 Section 7 Aerospace 1986 pp 63 68 External links EditDOD MIL STD 1750 standard DOD MIL STD 1750 standard PDF with updated Notice 1 21 May 1982 DOD MIL STD 1750 standard HTML with updated Notice 1 21 May 1982 Software Vendor Information Specification and vendor information Ada83 compiler for the 1750A processor IDE Ada95 EC and ANSI C compilers for the 1750A processor Ada and ANSI C compilers FlightLinux Project Target Architecture Technical Report References to use in spacecraft Dynex Semiconductor MA31750 Processor Pyramid Semiconductor P1750A SOS Processor Retrieved from https en wikipedia org w index php title MIL STD 1750A amp oldid 1117379764, wikipedia, wiki, book, books, library,
