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After simulation the RTL description must be synthesized to fit in the final hardware (e.g. FPGA, ASIC). This step brings a lot of uncertainties because the real hardware is normally not as ideal as the simulation model. The differences between real world and simulation are a major reason why emulation is used in hardware design.
Generally the simulation and emulation environment are two independent systems. Semulation is a symbiosis of both methods. In semulation one part of a hardware design is processed sequential in software (e.g. the testbench) while the other part is emulated.
An example design flow for semulation is depicted in the following block chart:
The database holds the design and testbench files and the information about the block whether it will be simulated or emulated. The left part shows the normal simulation path where the design files must be compiled for an HDL simulator. The right part of the state chart handles the flow for the emulation system. Design files for the FPGA must be synthesized to the appropriate target technology. A major point in semulation is the connection between the emulation system and the HDL simulator. The interface is necessary for the simulator to handle the connected hardware.
Advantages of Semulationedit
Simulation acceleration: Simulating huge designs with an HDL simulator is a tedious task. When the designer transfers parts of the design to an emulation system and co-simulates them with the HDL simulation, the simulation run times can be decreased.
Using real hardware early in the design flow.
Referencesedit
D. Scheurer and S. Reichör, SEmulation: Turbocharging the FPGA Development Process. White Paper, Altera Corporation
External linksedit
SEmulation Technology Combines ReConfigurable Computing-based Simulation and Emulation into a Single Platform for RTL Design Verification
SEmulator
SDC to Showcase SEmulation for FPGA Development at Embedded Masterclass
Semulation in EETimes
April 12, 2024
semulation, this, article, multiple, issues, please, help, improve, discuss, these, issues, talk, page, learn, when, remove, these, template, messages, this, article, relies, largely, entirely, single, source, relevant, discussion, found, talk, page, please, h. This article has multiple issues Please help improve it or discuss these issues on the talk page Learn how and when to remove these template messages This article relies largely or entirely on a single source Relevant discussion may be found on the talk page Please help improve this article by introducing citations to additional sources Find sources Semulation news newspapers books scholar JSTOR February 2021 This article is written like a research paper or scientific journal Please help improve the article by rewriting it in encyclopedic style and simplify overly technical phrases February 2021 Learn how and when to remove this template message The topic of this article may not meet Wikipedia s general notability guideline Please help to demonstrate the notability of the topic by citing reliable secondary sources that are independent of the topic and provide significant coverage of it beyond a mere trivial mention If notability cannot be shown the article is likely to be merged redirected or deleted Find sources Semulation news newspapers books scholar JSTOR July 2023 Learn how and when to remove this template message Learn how and when to remove this template message Semulation is a computer science related portmanteau of simulation and emulation signifying the process of controlling an emulation through a simulator Contents 1 Semulation in computer science 1 1 Advantages of Semulation 2 References 3 External linksSemulation in computer science editDigital hardware is described using hardware description languages HDL like VHDL Verilog or System Verilog These descriptions are simulated together with a problem specific testbench The initial functional verification of most IP designs is done via simulation at register transfer level RTL or gate level In an event driven simulation method the code must be processed sequential by a CPU because a normal computer is not able to process the implemented hardware parallel This sequential approach leads to long simulation times especially in complex systems on chip SoC designs After simulation the RTL description must be synthesized to fit in the final hardware e g FPGA ASIC This step brings a lot of uncertainties because the real hardware is normally not as ideal as the simulation model The differences between real world and simulation are a major reason why emulation is used in hardware design Generally the simulation and emulation environment are two independent systems Semulation is a symbiosis of both methods In semulation one part of a hardware design is processed sequential in software e g the testbench while the other part is emulated An example design flow for semulation is depicted in the following block chart nbsp The database holds the design and testbench files and the information about the block whether it will be simulated or emulated The left part shows the normal simulation path where the design files must be compiled for an HDL simulator The right part of the state chart handles the flow for the emulation system Design files for the FPGA must be synthesized to the appropriate target technology A major point in semulation is the connection between the emulation system and the HDL simulator The interface is necessary for the simulator to handle the connected hardware Advantages of Semulation edit Simulation acceleration Simulating huge designs with an HDL simulator is a tedious task When the designer transfers parts of the design to an emulation system and co simulates them with the HDL simulation the simulation run times can be decreased Using real hardware early in the design flow References editD Scheurer and S Reichor SEmulation Turbocharging the FPGA Development Process White Paper Altera CorporationExternal links editSEmulation Technology Combines ReConfigurable Computing based Simulation and Emulation into a Single Platform for RTL Design Verification SEmulator SDC to Showcase SEmulation for FPGA Development at Embedded Masterclass Semulation in EETimes Retrieved from https en wikipedia org w index php title Semulation amp oldid 1165309492, wikipedia, wiki, book, books, library,
