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Reconfigurable computing

March 03, 2023

Reconfigurable computing is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow. On the other hand, the main difference from custom hardware, i.e. application-specific integrated circuits (ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric.

History

The concept of reconfigurable computing has existed since the 1960s, when Gerald Estrin's paper proposed the concept of a computer made of a standard processor and an array of "reconfigurable" hardware.[1][2] The main processor would control the behavior of the reconfigurable hardware. The latter would then be tailored to perform a specific task, such as image processing or pattern matching, as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task. This resulted in a hybrid computer structure combining the flexibility of software with the speed of hardware.

In the 1980s and 1990s there was a renaissance in this area of research with many proposed reconfigurable architectures developed in industry and academia,[3] such as: Copacobana, Matrix, GARP,[4] Elixent, NGEN,[5] Polyp,[6] MereGen,[7] PACT XPP, Silicon Hive, Montium, Pleiades, Morphosys, and PiCoGA.[8] Such designs were feasible due to the constant progress of silicon technology that let complex designs be implemented on one chip. Some of these massively parallel reconfigurable computers were built primarily for special subdomains such as molecular evolution, neural or image processing. The world's first commercial reconfigurable computer, the Algotronix CHS2X4, was completed in 1991. It was not a commercial success, but was promising enough that Xilinx (the inventor of the Field-Programmable Gate Array, FPGA) bought the technology and hired the Algotronix staff.[9] Later machines enabled first demonstrations of scientific principles, such as the spontaneous spatial self-organisation of genetic coding with MereGen.[10]

Theories

Tredennick's Classification

Table 1: Nick Tredennick’s Paradigm Classification Scheme
Early Historic Computers:
  Programming Source
Resources fixed none
Algorithms fixed none
von Neumann Computer:
  Programming Source
Resources fixed none
Algorithms variable Software (instruction streams)
Reconfigurable Computing Systems:
  Programming Source
Resources variable Configware (configuration)
Algorithms variable Flowware (data streams)

The fundamental model of the reconfigurable computing machine paradigm, the data-stream-based anti machine is well illustrated by the differences to other machine paradigms that were introduced earlier, as shown by Nick Tredennick's following classification scheme of computing paradigms (see "Table 1: Nick Tredennick’s Paradigm Classification Scheme").[11]

Hartenstein's Xputer

Main article: Xputer

Computer scientist Reiner Hartenstein describes reconfigurable computing in terms of an anti-machine that, according to him, represents a fundamental paradigm shift away from the more conventional von Neumann machine.[12] Hartenstein calls it Reconfigurable Computing Paradox, that software-to-configware (software-to-FPGA) migration results in reported speed-up factors of up to more than four orders of magnitude, as well as a reduction in electricity consumption by up to almost four orders of magnitude—although the technological parameters of FPGAs are behind the Gordon Moore curve by about four orders of magnitude, and the clock frequency is substantially lower than that of microprocessors. This paradox is partly explained by the Von Neumann syndrome.

High-performance computing

High-Performance Reconfigurable Computing (HPRC) is a computer architecture combining reconfigurable computing-based accelerators like field-programmable gate array with CPUs or multi-core processors.

The increase of logic in an FPGA has enabled larger and more complex algorithms to be programmed into the FPGA. The attachment of such an FPGA to a modern CPU over a high speed bus, like PCI express, has enabled the configurable logic to act more like a coprocessor rather than a peripheral. This has brought reconfigurable computing into the high-performance computing sphere.

Furthermore, by replicating an algorithm on an FPGA or the use of a multiplicity of FPGAs has enabled reconfigurable SIMD systems to be produced where several computational devices can concurrently operate on different data, which is highly parallel computing.

This heterogeneous systems technique is used in computing research and especially in supercomputing.[13] A 2008 paper reported speed-up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude.[14] Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators.[citation needed] One research area is the twin-paradigm programming tool flow productivity obtained for such heterogeneous systems.[15]

The US National Science Foundation has a center for high-performance reconfigurable computing (CHREC).[16] In April 2011 the fourth Many-core and Reconfigurable Supercomputing Conference was held in Europe.[17]

Commercial high-performance reconfigurable computing systems are beginning to emerge with the announcement of IBM integrating FPGAs with its IBM Power microprocessors.[18]

Partial re-configuration

Partial re-configuration is the process of changing a portion of reconfigurable hardware circuitry while the other portion keeps its former configuration. Field programmable gate arrays are often used as a support to partial reconfiguration.

Electronic hardware, like software, can be designed modularly, by creating subcomponents and then higher-level components to instantiate them. In many cases it is useful to be able to swap out one or several of these subcomponents while the FPGA is still operating.

Normally, reconfiguring an FPGA requires it to be held in reset while an external controller reloads a design onto it. Partial reconfiguration allows for critical parts of the design to continue operating while a controller either on the FPGA or off of it loads a partial design into a reconfigurable module. Partial reconfiguration also can be used to save space for multiple designs by only storing the partial designs that change between designs.[19]

A common example for when partial reconfiguration would be useful is the case of a communication device. If the device is controlling multiple connections, some of which require encryption, it would be useful to be able to load different encryption cores without bringing the whole controller down.

Partial reconfiguration is not supported on all FPGAs. A special software flow with emphasis on modular design is required. Typically the design modules are built along well defined boundaries inside the FPGA that require the design to be specially mapped to the internal hardware.

From the functionality of the design, partial reconfiguration can be divided into two groups:[20]

  • dynamic partial reconfiguration, also known as an active partial reconfiguration - permits to change the part of the device while the rest of an FPGA is still running;
  • static partial reconfiguration - the device is not active during the reconfiguration process. While the partial data is sent into the FPGA, the rest of the device is stopped (in the shutdown mode) and brought up after the configuration is completed.

Current systems

Computer emulation

 
An FPGA board is being used to recreate the Vector-06C computer

With the advent of affordable FPGA boards, students' and hobbyists' projects seek to recreate vintage computers or implement more novel architectures.[21][22][23] Such projects are built with reconfigurable hardware (FPGAs), and some devices support emulation of multiple vintage computers using a single reconfigurable hardware (C-One).

COPACOBANA

A fully FPGA-based computer is the COPACOBANA, the Cost Optimized Codebreaker and Analyzer and its successor RIVYERA. A spin-off company SciEngines GmbH of the COPACOBANA-Project of the Universities of Bochum and Kiel in Germany continues the development of fully FPGA-based computers.

Mitrionics

Mitrionics has developed a SDK that enables software written using a single assignment language to be compiled and executed on FPGA-based computers. The Mitrion-C software language and Mitrion processor enable software developers to write and execute applications on FPGA-based computers in the same manner as with other computing technologies, such as graphical processing units (“GPUs”), cell-based processors, parallel processing units (“PPUs”), multi-core CPUs, and traditional single-core CPU clusters. (out of business)

National Instruments

National Instruments have developed a hybrid embedded computing system called CompactRIO. It consists of reconfigurable chassis housing the user-programmable FPGA, hot swappable I/O modules, real-time controller for deterministic communication and processing, and graphical LabVIEW software for rapid RT and FPGA programming.

Xilinx

Xilinx has developed two styles of partial reconfiguration of FPGA devices: module-based and difference-based. Module-based partial reconfiguration permits to reconfigure distinct modular parts of the design, while difference-based partial reconfiguration can be used when a small change is made to a design.

Intel

Intel[24] supports partial reconfiguration of their FPGA devices on 28 nm devices such as Stratix V,[25] and on the 20 nm Arria 10 devices.[26] The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create physical partitions of the FPGA that can be reconfigured[27] at runtime while the remainder of the design continues to operate. The Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration.

Classification of systems

As an emerging field, classifications of reconfigurable architectures are still being developed and refined as new architectures are developed; no unifying taxonomy has been suggested to date. However, several recurring parameters can be used to classify these systems.

Granularity

The granularity of the reconfigurable logic is defined as the size of the smallest functional unit (configurable logic block, CLB) that is addressed by the mapping tools. High granularity, which can also be known as fine-grained, often implies a greater flexibility when implementing algorithms into the hardware. However, there is a penalty associated with this in terms of increased power, area and delay due to greater quantity of routing required per computation. Fine-grained architectures work at the bit-level manipulation level; whilst coarse grained processing elements (reconfigurable datapath unit, rDPU) are better optimised for standard data path applications. One of the drawbacks of coarse grained architectures are that they tend to lose some of their utilisation and performance if they need to perform smaller computations than their granularity provides, for example for a one bit add on a four bit wide functional unit would waste three bits. This problem can be solved by having a coarse grain array (reconfigurable datapath array, rDPA) and a FPGA on the same chip.

Coarse-grained architectures (rDPA) are intended for the implementation for algorithms needing word-width data paths (rDPU). As their functional blocks are optimized for large computations and typically comprise word wide arithmetic logic units (ALU), they will perform these computations more quickly and with more power efficiency than a set of interconnected smaller functional units; this is due to the connecting wires being shorter, resulting in less wire capacitance and hence faster and lower power designs. A potential undesirable consequence of having larger computational blocks is that when the size of operands may not match the algorithm an inefficient utilisation of resources can result. Often the type of applications to be run are known in advance allowing the logic, memory and routing resources to be tailored to enhance the performance of the device whilst still providing a certain level of flexibility for future adaptation. Examples of this are domain specific arrays aimed at gaining better performance in terms of power, area, throughput than their more generic finer grained FPGA cousins by reducing their flexibility.

Rate of reconfiguration

Configuration of these reconfigurable systems can happen at deployment time, between execution phases or during execution. In a typical reconfigurable system, a bit stream is used to program the device at deployment time. Fine grained systems by their own nature require greater configuration time than more coarse-grained architectures due to more elements needing to be addressed and programmed. Therefore, more coarse-grained architectures gain from potential lower energy requirements, as less information is transferred and utilised. Intuitively, the slower the rate of reconfiguration the smaller the power consumption as the associated energy cost of reconfiguration are amortised over a longer period of time. Partial re-configuration aims to allow part of the device to be reprogrammed while another part is still performing active computation. Partial re-configuration allows smaller reconfigurable bit streams thus not wasting energy on transmitting redundant information in the bit stream. Compression of the bit stream is possible but careful analysis is to be carried out to ensure that the energy saved by using smaller bit streams is not outweighed by the computation needed to decompress the data.

Host coupling

Often the reconfigurable array is used as a processing accelerator attached to a host processor. The level of coupling determines the type of data transfers, latency, power, throughput and overheads involved when utilising the reconfigurable logic. Some of the most intuitive designs use a peripheral bus to provide a coprocessor like arrangement for the reconfigurable array. However, there have also been implementations where the reconfigurable fabric is much closer to the processor, some are even implemented into the data path, utilising the processor registers. The job of the host processor is to perform the control functions, configure the logic, schedule data and to provide external interfacing.

Routing/interconnects

The flexibility in reconfigurable devices mainly comes from their routing interconnect. One style of interconnect made popular by FPGAs vendors, Xilinx and Altera are the island style layout, where blocks are arranged in an array with vertical and horizontal routing. A layout with inadequate routing may suffer from poor flexibility and resource utilisation, therefore providing limited performance. If too much interconnect is provided this requires more transistors than necessary and thus more silicon area, longer wires and more power consumption.

Challenges for operating systems

One of the key challenges for reconfigurable computing is to enable higher design productivity and provide an easier way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system.[28]

One of the major tasks of an operating system is to hide the hardware and present programs (and their programmers) with nice, clean, elegant, and consistent abstractions to work with instead. In other words, the two main tasks of an operating system are abstraction and resource management.[28]

Abstraction is a powerful mechanism to handle complex and different (hardware) tasks in a well-defined and common manner. One of the most elementary OS abstractions is a process. A process is a running application that has the perception (provided by the OS) that it is running on its own on the underlying virtual hardware. This can be relaxed by the concept of threads, allowing different tasks to run concurrently on this virtual hardware to exploit task level parallelism. To allow different processes and threads to coordinate their work, communication and synchronization methods have to be provided by the OS.[28]

In addition to abstraction, resource management of the underlying hardware components is necessary because the virtual computers provided to the processes and threads by the operating system need to share available physical resources (processors, memory, and devices) spatially and temporarily.[28]

See also

References

  1. ^ Estrin, G (2002). "Reconfigurable computer origins: the UCLA fixed-plus-variable (F+V) structure computer". IEEE Ann. Hist. Comput. 24 (4): 3–9. doi:10.1109/MAHC.2002.1114865.
  2. ^ Estrin, G., "Organization of Computer Systems—The Fixed Plus Variable Structure Computer", Proc. Western Joint Computer Conf., Western Joint Computer Conference, New York, 1960, pp. 33–40.
  3. ^ C. Bobda: Introduction to Reconfigurable Computing: Architectures; Springer, 2007
  4. ^ Hauser, John R. and Wawrzynek, John, "Garp: A MIPS Processor with a Reconfigurable Coprocessor", Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97, April 16–18, 1997), pp. 24–33.
  5. ^ McCaskill, John S.; Chorongiewski, Harald; Mekelburg, Karsten; Tangen, Uwe; Gemm, Udo (1994-09-01). "NGEN — Configurable computer hardware to simulate long-time self-organization of biopolymers". Berichte der Bunsengesellschaft für Physikalische Chemie. 98 (9): 1114. doi:10.1002/bbpc.19940980906. ISSN 0005-9021.
  6. ^ Evolvable systems : from biology to hardware : second International Conference, ICES 98, Lausanne, Switzerland, September 23-25, 1998 : proceedings. Sipper, Moshe., Mange, Daniel, 1940-, Pérez-Uribe, Andrés., International Conference on Evolvable Systems (2nd : 1998 : Lausanne, Switzerland). Berlin: Springer. 1998. ISBN 978-3540649540. OCLC 39655211.{{cite book}}: CS1 maint: others (link)
  7. ^ Coupling of biological and electronic systems : proceedings of the 2nd Caesarium, Bonn, November 1-3, 2000. Hoffmann, K.-H. (Karl-Heinz). Berlin: Springer. 2002. ISBN 978-3540436997. OCLC 49750250.{{cite book}}: CS1 maint: others (link)
  8. ^ Campi, F.; Toma, M.; Lodi, A.; Cappelli, A.; Canegallo, R.; Guerrieri, R., "A VLIW processor with reconfigurable instruction set for embedded applications", Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, vol., no., pp. 250–491 vol. 1, 2003
  9. ^ Algotronix History
  10. ^ Füchslin, Rudolf M.; McCaskill, John S. (2001-07-31). "Evolutionary self-organization of cell-free genetic coding". Proceedings of the National Academy of Sciences. 98 (16): 9185–9190. Bibcode:2001PNAS...98.9185F. doi:10.1073/pnas.151253198. ISSN 0027-8424. PMC 55395. PMID 11470896.
  11. ^ N. Tredennick: The Case for Reconfigurable Computing; Microprocessor Report, Vol. 10 No. 10, 5 August 1996, pp 25–27.
  12. ^ Hartenstein, R. 2001. A decade of reconfigurable computing: a visionary retrospective. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2001) (Munich, Germany). W. Nebel and A. Jerraya, Eds. Design, Automation, and Test in Europe. IEEE Press, Piscataway, NJ, 642–649.
  13. ^ N. Voros, R. Nikolaos, A. Rosti, M. Hübner (editors): Dynamic System Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag, 2009
  14. ^ Tarek El-Ghazawi et al. (February 2008). "The promise of high-performance reconfigurable computing". IEEE Computer. 41 (2): 69–76. CiteSeerX 10.1.1.208.4031. doi:10.1109/MC.2008.65. S2CID 14469864.{{cite journal}}: CS1 maint: uses authors parameter (link)
  15. ^ Esam El-Araby; Ivan Gonzalez; Tarek El-Ghazawi (January 2009). "Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing". ACM Transactions on Reconfigurable Technology and Systems. 1 (4): 1–23. doi:10.1145/1462586.1462590. S2CID 10270587.
  16. ^ "NSF center for High-performance Reconfigurable Computing". official web site. Retrieved August 19, 2011.
  17. ^ . official web site. 2011. Archived from the original on October 12, 2010. Retrieved August 19, 2011.
  18. ^ "Altera and IBM Unveil FPGA-Accelerated POWER Systems". HPCwire. 2014-11-17. Retrieved 2014-12-14.
  19. ^ Wanta, Damian; Smolik, Waldemar T.; Kryszyn, Jacek; Wróblewski, Przemysław; Midura, Mateusz (2022). "A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System". Electronics. 11 (4): 545. doi:10.3390/electronics11040545.
  20. ^ Wiśniewski, Remigiusz (2009). Synthesis of compositional microprogram control units for programmable devices. Zielona Góra: University of Zielona Góra. p. 153. ISBN 978-83-7481-293-1.
  21. ^ "Apple2 FPGA". Retrieved 6 Sep 2012.
  22. ^ Niklaus Wirth. "The Design of a RISC Architecture and its Implementation with an FPGA" (PDF). Retrieved 6 Sep 2012.[dead link]
  23. ^ Jan Gray. "Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip" (PDF). Retrieved 6 Sep 2012.
  24. ^ "Intel completes acquisition of Altera". Retrieved 15 November 2016.
  25. ^ "Stratix V FPGAs: Ultimate Flexibility Through Partial and Dynamic Reconfiguration". Retrieved 15 November 2016.
  26. ^ "Intel Quartus Prime Software Productivity Tools and Features". Retrieved 15 November 2016.
  27. ^ "Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis" (PDF). Intel. pp. 4–1. Retrieved 15 November 2016.
  28. ^ a b c d Eckert, Marcel; Meyer, Dominik; Haase, Jan; Klauer, Bernd (2016-11-30). "Operating System Concepts for Reconfigurable Computing: Review and Survey". International Journal of Reconfigurable Computing. 2016: 1–11. doi:10.1155/2016/2478907. ISSN 1687-7195.   This article contains quotations from this source, which is available under the Creative Commons Attribution 4.0 International (CC BY 4.0) license.

Further reading

  • Cardoso, João M. P.; Hübner, Michael (Eds.), Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, Springer, 2011.
  • S. Hauck and A. DeHon, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing, Morgan Kaufmann, 2008.
  • J. Henkel, S. Parameswaran (editors): Designing Embedded Processors. A Low Power Perspective; Springer Verlag, March 2007
  • J. Teich (editor) et al.: Reconfigurable Computing Systems. Special Topic Issue of Journal it — Information Technology, Oldenbourg Verlag, Munich. Vol. 49(2007) Issue 3
  • T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, "Reconfigurable Computing: Architectures and Design Methods", IEEE Proceedings: Computer & Digital Techniques, Vol. 152, No. 2, March 2005, pp. 193–208.
  • A. Zomaya (editor): Handbook of Nature-Inspired and Innovative Computing: Integrating Classical Models with Emerging Technologies; Springer Verlag, 2006
  • J. M. Arnold and D. A. Buell, "VHDL programming on Splash 2," in More FPGAs, Will Moore and Wayne Luk, editors, Abingdon EE & CS Books, Oxford, England, 1994, pp. 182–191. (Proceedings,International Workshop on Field-Programmable Logic, Oxford, 1993.)
  • J. M. Arnold, D. A. Buell, D. Hoang, D. V. Pryor, N. Shirazi, M. R. Thistle, "Splash 2 and its applications, "Proceedings, International Conference on Computer Design, Cambridge, 1993, pp. 482–486.
  • D. A. Buell and Kenneth L. Pocek, "Custom computing machines: An introduction," The Journal of Supercomputing, v. 9, 1995, pp. 219–230.

External links

  • Lectures on Reconfigurable Computing at Brown University
  • ReCoBus-Builder project for easily implementing complex reconfigurable systems
  • DRESD (Dynamic Reconfigurability in Embedded System Design) research project

March 03, 2023
reconfigurable, computing, this, article, technical, most, readers, understand, please, help, improve, make, understandable, experts, without, removing, technical, details, 2009, learn, when, remove, this, template, message, computer, architecture, combining, . This article may be too technical for most readers to understand Please help improve it to make it understandable to non experts without removing the technical details May 2009 Learn how and when to remove this template message Reconfigurable computing is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field programmable gate arrays FPGAs The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow On the other hand the main difference from custom hardware i e application specific integrated circuits ASICs is the possibility to adapt the hardware during runtime by loading a new circuit on the reconfigurable fabric Contents 1 History 2 Theories 2 1 Tredennick s Classification 2 2 Hartenstein s Xputer 3 High performance computing 4 Partial re configuration 5 Current systems 5 1 Computer emulation 5 2 COPACOBANA 5 3 Mitrionics 5 4 National Instruments 5 5 Xilinx 5 6 Intel 6 Classification of systems 6 1 Granularity 6 2 Rate of reconfiguration 6 3 Host coupling 6 4 Routing interconnects 7 Challenges for operating systems 8 See also 9 References 10 Further reading 11 External linksHistory EditThe concept of reconfigurable computing has existed since the 1960s when Gerald Estrin s paper proposed the concept of a computer made of a standard processor and an array of reconfigurable hardware 1 2 The main processor would control the behavior of the reconfigurable hardware The latter would then be tailored to perform a specific task such as image processing or pattern matching as quickly as a dedicated piece of hardware Once the task was done the hardware could be adjusted to do some other task This resulted in a hybrid computer structure combining the flexibility of software with the speed of hardware In the 1980s and 1990s there was a renaissance in this area of research with many proposed reconfigurable architectures developed in industry and academia 3 such as Copacobana Matrix GARP 4 Elixent NGEN 5 Polyp 6 MereGen 7 PACT XPP Silicon Hive Montium Pleiades Morphosys and PiCoGA 8 Such designs were feasible due to the constant progress of silicon technology that let complex designs be implemented on one chip Some of these massively parallel reconfigurable computers were built primarily for special subdomains such as molecular evolution neural or image processing The world s first commercial reconfigurable computer the Algotronix CHS2X4 was completed in 1991 It was not a commercial success but was promising enough that Xilinx the inventor of the Field Programmable Gate Array FPGA bought the technology and hired the Algotronix staff 9 Later machines enabled first demonstrations of scientific principles such as the spontaneous spatial self organisation of genetic coding with MereGen 10 Theories EditTredennick s Classification Edit Table 1 Nick Tredennick s Paradigm Classification Scheme Early Historic Computers Programming SourceResources fixed noneAlgorithms fixed nonevon Neumann Computer Programming SourceResources fixed noneAlgorithms variable Software instruction streams Reconfigurable Computing Systems Programming SourceResources variable Configware configuration Algorithms variable Flowware data streams The fundamental model of the reconfigurable computing machine paradigm the data stream based anti machine is well illustrated by the differences to other machine paradigms that were introduced earlier as shown by Nick Tredennick s following classification scheme of computing paradigms see Table 1 Nick Tredennick s Paradigm Classification Scheme 11 Hartenstein s Xputer Edit Main article Xputer Computer scientist Reiner Hartenstein describes reconfigurable computing in terms of an anti machine that according to him represents a fundamental paradigm shift away from the more conventional von Neumann machine 12 Hartenstein calls it Reconfigurable Computing Paradox that software to configware software to FPGA migration results in reported speed up factors of up to more than four orders of magnitude as well as a reduction in electricity consumption by up to almost four orders of magnitude although the technological parameters of FPGAs are behind the Gordon Moore curve by about four orders of magnitude and the clock frequency is substantially lower than that of microprocessors This paradox is partly explained by the Von Neumann syndrome High performance computing EditHigh Performance Reconfigurable Computing HPRC is a computer architecture combining reconfigurable computing based accelerators like field programmable gate array with CPUs or multi core processors The increase of logic in an FPGA has enabled larger and more complex algorithms to be programmed into the FPGA The attachment of such an FPGA to a modern CPU over a high speed bus like PCI express has enabled the configurable logic to act more like a coprocessor rather than a peripheral This has brought reconfigurable computing into the high performance computing sphere Furthermore by replicating an algorithm on an FPGA or the use of a multiplicity of FPGAs has enabled reconfigurable SIMD systems to be produced where several computational devices can concurrently operate on different data which is highly parallel computing This heterogeneous systems technique is used in computing research and especially in supercomputing 13 A 2008 paper reported speed up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude 14 Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators citation needed One research area is the twin paradigm programming tool flow productivity obtained for such heterogeneous systems 15 The US National Science Foundation has a center for high performance reconfigurable computing CHREC 16 In April 2011 the fourth Many core and Reconfigurable Supercomputing Conference was held in Europe 17 Commercial high performance reconfigurable computing systems are beginning to emerge with the announcement of IBM integrating FPGAs with its IBM Power microprocessors 18 Partial re configuration EditPartial re configuration is the process of changing a portion of reconfigurable hardware circuitry while the other portion keeps its former configuration Field programmable gate arrays are often used as a support to partial reconfiguration Electronic hardware like software can be designed modularly by creating subcomponents and then higher level components to instantiate them In many cases it is useful to be able to swap out one or several of these subcomponents while the FPGA is still operating Normally reconfiguring an FPGA requires it to be held in reset while an external controller reloads a design onto it Partial reconfiguration allows for critical parts of the design to continue operating while a controller either on the FPGA or off of it loads a partial design into a reconfigurable module Partial reconfiguration also can be used to save space for multiple designs by only storing the partial designs that change between designs 19 A common example for when partial reconfiguration would be useful is the case of a communication device If the device is controlling multiple connections some of which require encryption it would be useful to be able to load different encryption cores without bringing the whole controller down Partial reconfiguration is not supported on all FPGAs A special software flow with emphasis on modular design is required Typically the design modules are built along well defined boundaries inside the FPGA that require the design to be specially mapped to the internal hardware From the functionality of the design partial reconfiguration can be divided into two groups 20 dynamic partial reconfiguration also known as an active partial reconfiguration permits to change the part of the device while the rest of an FPGA is still running static partial reconfiguration the device is not active during the reconfiguration process While the partial data is sent into the FPGA the rest of the device is stopped in the shutdown mode and brought up after the configuration is completed Current systems EditComputer emulation Edit An FPGA board is being used to recreate the Vector 06C computer With the advent of affordable FPGA boards students and hobbyists projects seek to recreate vintage computers or implement more novel architectures 21 22 23 Such projects are built with reconfigurable hardware FPGAs and some devices support emulation of multiple vintage computers using a single reconfigurable hardware C One COPACOBANA Edit A fully FPGA based computer is the COPACOBANA the Cost Optimized Codebreaker and Analyzer and its successor RIVYERA A spin off company SciEngines GmbH of the COPACOBANA Project of the Universities of Bochum and Kiel in Germany continues the development of fully FPGA based computers Mitrionics Edit Mitrionics has developed a SDK that enables software written using a single assignment language to be compiled and executed on FPGA based computers The Mitrion C software language and Mitrion processor enable software developers to write and execute applications on FPGA based computers in the same manner as with other computing technologies such as graphical processing units GPUs cell based processors parallel processing units PPUs multi core CPUs and traditional single core CPU clusters out of business National Instruments Edit National Instruments have developed a hybrid embedded computing system called CompactRIO It consists of reconfigurable chassis housing the user programmable FPGA hot swappable I O modules real time controller for deterministic communication and processing and graphical LabVIEW software for rapid RT and FPGA programming Xilinx Edit Xilinx has developed two styles of partial reconfiguration of FPGA devices module based and difference based Module based partial reconfiguration permits to reconfigure distinct modular parts of the design while difference based partial reconfiguration can be used when a small change is made to a design Intel Edit Intel 24 supports partial reconfiguration of their FPGA devices on 28 nm devices such as Stratix V 25 and on the 20 nm Arria 10 devices 26 The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create physical partitions of the FPGA that can be reconfigured 27 at runtime while the remainder of the design continues to operate The Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration Classification of systems EditThis section needs additional citations for verification Please help improve this article by adding citations to reliable sources Unsourced material may be challenged and removed January 2015 Learn how and when to remove this template message This section possibly contains original research Please improve it by verifying the claims made and adding inline citations Statements consisting only of original research should be removed January 2015 Learn how and when to remove this template message As an emerging field classifications of reconfigurable architectures are still being developed and refined as new architectures are developed no unifying taxonomy has been suggested to date However several recurring parameters can be used to classify these systems Granularity Edit The granularity of the reconfigurable logic is defined as the size of the smallest functional unit configurable logic block CLB that is addressed by the mapping tools High granularity which can also be known as fine grained often implies a greater flexibility when implementing algorithms into the hardware However there is a penalty associated with this in terms of increased power area and delay due to greater quantity of routing required per computation Fine grained architectures work at the bit level manipulation level whilst coarse grained processing elements reconfigurable datapath unit rDPU are better optimised for standard data path applications One of the drawbacks of coarse grained architectures are that they tend to lose some of their utilisation and performance if they need to perform smaller computations than their granularity provides for example for a one bit add on a four bit wide functional unit would waste three bits This problem can be solved by having a coarse grain array reconfigurable datapath array rDPA and a FPGA on the same chip Coarse grained architectures rDPA are intended for the implementation for algorithms needing word width data paths rDPU As their functional blocks are optimized for large computations and typically comprise word wide arithmetic logic units ALU they will perform these computations more quickly and with more power efficiency than a set of interconnected smaller functional units this is due to the connecting wires being shorter resulting in less wire capacitance and hence faster and lower power designs A potential undesirable consequence of having larger computational blocks is that when the size of operands may not match the algorithm an inefficient utilisation of resources can result Often the type of applications to be run are known in advance allowing the logic memory and routing resources to be tailored to enhance the performance of the device whilst still providing a certain level of flexibility for future adaptation Examples of this are domain specific arrays aimed at gaining better performance in terms of power area throughput than their more generic finer grained FPGA cousins by reducing their flexibility Rate of reconfiguration Edit Configuration of these reconfigurable systems can happen at deployment time between execution phases or during execution In a typical reconfigurable system a bit stream is used to program the device at deployment time Fine grained systems by their own nature require greater configuration time than more coarse grained architectures due to more elements needing to be addressed and programmed Therefore more coarse grained architectures gain from potential lower energy requirements as less information is transferred and utilised Intuitively the slower the rate of reconfiguration the smaller the power consumption as the associated energy cost of reconfiguration are amortised over a longer period of time Partial re configuration aims to allow part of the device to be reprogrammed while another part is still performing active computation Partial re configuration allows smaller reconfigurable bit streams thus not wasting energy on transmitting redundant information in the bit stream Compression of the bit stream is possible but careful analysis is to be carried out to ensure that the energy saved by using smaller bit streams is not outweighed by the computation needed to decompress the data Host coupling Edit Often the reconfigurable array is used as a processing accelerator attached to a host processor The level of coupling determines the type of data transfers latency power throughput and overheads involved when utilising the reconfigurable logic Some of the most intuitive designs use a peripheral bus to provide a coprocessor like arrangement for the reconfigurable array However there have also been implementations where the reconfigurable fabric is much closer to the processor some are even implemented into the data path utilising the processor registers The job of the host processor is to perform the control functions configure the logic schedule data and to provide external interfacing Routing interconnects Edit The flexibility in reconfigurable devices mainly comes from their routing interconnect One style of interconnect made popular by FPGAs vendors Xilinx and Altera are the island style layout where blocks are arranged in an array with vertical and horizontal routing A layout with inadequate routing may suffer from poor flexibility and resource utilisation therefore providing limited performance If too much interconnect is provided this requires more transistors than necessary and thus more silicon area longer wires and more power consumption Challenges for operating systems EditOne of the key challenges for reconfigurable computing is to enable higher design productivity and provide an easier way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts One way of doing this is to provide standardization and abstraction usually supported and enforced by an operating system 28 One of the major tasks of an operating system is to hide the hardware and present programs and their programmers with nice clean elegant and consistent abstractions to work with instead In other words the two main tasks of an operating system are abstraction and resource management 28 Abstraction is a powerful mechanism to handle complex and different hardware tasks in a well defined and common manner One of the most elementary OS abstractions is a process A process is a running application that has the perception provided by the OS that it is running on its own on the underlying virtual hardware This can be relaxed by the concept of threads allowing different tasks to run concurrently on this virtual hardware to exploit task level parallelism To allow different processes and threads to coordinate their work communication and synchronization methods have to be provided by the OS 28 In addition to abstraction resource management of the underlying hardware components is necessary because the virtual computers provided to the processes and threads by the operating system need to share available physical resources processors memory and devices spatially and temporarily 28 See also EditComputing with Memory Glossary of reconfigurable computing iLAND project M Labs One chip MSX PipeRench PSoC SprinterReferences Edit Estrin G 2002 Reconfigurable computer origins the UCLA fixed plus variable F V structure computer IEEE Ann Hist Comput 24 4 3 9 doi 10 1109 MAHC 2002 1114865 Estrin G Organization of Computer Systems The Fixed Plus Variable Structure Computer Proc Western Joint Computer Conf Western Joint Computer Conference New York 1960 pp 33 40 C Bobda Introduction to Reconfigurable Computing Architectures Springer 2007 Hauser John R and Wawrzynek John Garp A MIPS Processor with a Reconfigurable Coprocessor Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines FCCM 97 April 16 18 1997 pp 24 33 McCaskill John S Chorongiewski Harald Mekelburg Karsten Tangen Uwe Gemm Udo 1994 09 01 NGEN Configurable computer hardware to simulate long time self organization of biopolymers Berichte der Bunsengesellschaft fur Physikalische Chemie 98 9 1114 doi 10 1002 bbpc 19940980906 ISSN 0005 9021 Evolvable systems from biology to hardware second International Conference ICES 98 Lausanne Switzerland September 23 25 1998 proceedings Sipper Moshe Mange Daniel 1940 Perez Uribe Andres International Conference on Evolvable Systems 2nd 1998 Lausanne Switzerland Berlin Springer 1998 ISBN 978 3540649540 OCLC 39655211 a href Template Cite book html title Template Cite book cite book a CS1 maint others link Coupling of biological and electronic systems proceedings of the 2nd Caesarium Bonn November 1 3 2000 Hoffmann K H Karl Heinz Berlin Springer 2002 ISBN 978 3540436997 OCLC 49750250 a href Template Cite book html title Template Cite book cite book a CS1 maint others link Campi F Toma M Lodi A Cappelli A Canegallo R Guerrieri R A VLIW processor with reconfigurable instruction set for embedded applications Solid State Circuits Conference 2003 Digest of Technical Papers ISSCC 2003 IEEE International vol no pp 250 491 vol 1 2003 Algotronix History Fuchslin Rudolf M McCaskill John S 2001 07 31 Evolutionary self organization of cell free genetic coding Proceedings of the National Academy of Sciences 98 16 9185 9190 Bibcode 2001PNAS 98 9185F doi 10 1073 pnas 151253198 ISSN 0027 8424 PMC 55395 PMID 11470896 N Tredennick The Case for Reconfigurable Computing Microprocessor Report Vol 10 No 10 5 August 1996 pp 25 27 Hartenstein R 2001 A decade of reconfigurable computing a visionary retrospective In Proceedings of the Conference on Design Automation and Test in Europe DATE 2001 Munich Germany W Nebel and A Jerraya Eds Design Automation and Test in Europe IEEE Press Piscataway NJ 642 649 N Voros R Nikolaos A Rosti M Hubner editors Dynamic System Reconfiguration in Heterogeneous Platforms The MORPHEUS Approach Springer Verlag 2009 Tarek El Ghazawi et al February 2008 The promise of high performance reconfigurable computing IEEE Computer 41 2 69 76 CiteSeerX 10 1 1 208 4031 doi 10 1109 MC 2008 65 S2CID 14469864 a href Template Cite journal html title Template Cite journal cite journal a CS1 maint uses authors parameter link Esam El Araby Ivan Gonzalez Tarek El Ghazawi January 2009 Exploiting Partial Runtime Reconfiguration for High Performance Reconfigurable Computing ACM Transactions on Reconfigurable Technology and Systems 1 4 1 23 doi 10 1145 1462586 1462590 S2CID 10270587 NSF center for High performance Reconfigurable Computing official web site Retrieved August 19 2011 Many Core and Reconfigurable Supercomputing Conference official web site 2011 Archived from the original on October 12 2010 Retrieved August 19 2011 Altera and IBM Unveil FPGA Accelerated POWER Systems HPCwire 2014 11 17 Retrieved 2014 12 14 Wanta Damian Smolik Waldemar T Kryszyn Jacek Wroblewski Przemyslaw Midura Mateusz 2022 A Run Time Reconfiguration Method for an FPGA Based Electrical Capacitance Tomography System Electronics 11 4 545 doi 10 3390 electronics11040545 Wisniewski Remigiusz 2009 Synthesis of compositional microprogram control units for programmable devices Zielona Gora University of Zielona Gora p 153 ISBN 978 83 7481 293 1 Apple2 FPGA Retrieved 6 Sep 2012 Niklaus Wirth The Design of a RISC Architecture and its Implementation with an FPGA PDF Retrieved 6 Sep 2012 dead link Jan Gray Designing a Simple FPGA Optimized RISC CPU and System on a Chip PDF Retrieved 6 Sep 2012 Intel completes acquisition of Altera Retrieved 15 November 2016 Stratix V FPGAs Ultimate Flexibility Through Partial and Dynamic Reconfiguration Retrieved 15 November 2016 Intel Quartus Prime Software Productivity Tools and Features Retrieved 15 November 2016 Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis PDF Intel pp 4 1 Retrieved 15 November 2016 a b c d Eckert Marcel Meyer Dominik Haase Jan Klauer Bernd 2016 11 30 Operating System Concepts for Reconfigurable Computing Review and Survey International Journal of Reconfigurable Computing 2016 1 11 doi 10 1155 2016 2478907 ISSN 1687 7195 This article contains quotations from this source which is available under the Creative Commons Attribution 4 0 International CC BY 4 0 license Further reading EditCardoso Joao M P Hubner Michael Eds Reconfigurable Computing From FPGAs to Hardware Software Codesign Springer 2011 S Hauck and A DeHon Reconfigurable Computing The Theory and Practice of FPGA Based Computing Morgan Kaufmann 2008 J Henkel S Parameswaran editors Designing Embedded Processors A Low Power Perspective Springer Verlag March 2007 J Teich editor et al Reconfigurable Computing Systems Special Topic Issue of Journal it Information Technology Oldenbourg Verlag Munich Vol 49 2007 Issue 3 T J Todman G A Constantinides S J E Wilton O Mencer W Luk and P Y K Cheung Reconfigurable Computing Architectures and Design Methods IEEE Proceedings Computer amp Digital Techniques Vol 152 No 2 March 2005 pp 193 208 A Zomaya editor Handbook of Nature Inspired and Innovative Computing Integrating Classical Models with Emerging Technologies Springer Verlag 2006 J M Arnold and D A Buell VHDL programming on Splash 2 in More FPGAs Will Moore and Wayne Luk editors Abingdon EE amp CS Books Oxford England 1994 pp 182 191 Proceedings International Workshop on Field Programmable Logic Oxford 1993 J M Arnold D A Buell D Hoang D V Pryor N Shirazi M R Thistle Splash 2 and its applications Proceedings International Conference on Computer Design Cambridge 1993 pp 482 486 D A Buell and Kenneth L Pocek Custom computing machines An introduction The Journal of Supercomputing v 9 1995 pp 219 230 External links EditLectures on Reconfigurable Computing at Brown University Introduction to Dynamic Partial Reconfiguration ReCoBus Builder project for easily implementing complex reconfigurable systems DRESD Dynamic Reconfigurability in Embedded System Design research project Retrieved from https en wikipedia org w index php title Reconfigurable computing amp oldid 1139990393, wikipedia, wiki, book, books, library,

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