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Wikipedia

FMA instruction set

January 06, 2023

Wikibooks has a book on the topic of: X86 Assembly/AVX, AVX2, FMA3, FMA4

The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations.[1] There are two variants:

Instructions

FMA3 and FMA4 instructions have almost identical functionality, but are not compatible. Both contain fused multiply–add (FMA) instructions for floating-point scalar and SIMD operations, but FMA3 instructions have three operands, while FMA4 ones have four. The FMA operation has the form d = round(a · b + c), where the round function performs a rounding to allow the result to fit within the destination register if there are too many significant bits to fit within the destination.

The four-operand form (FMA4) allows a, b, c and d to be four different registers, while the three-operand form (FMA3) requires that d be the same register as a, b or c. The three-operand form makes the code shorter and the hardware implementation slightly simpler, while the four-operand form provides more programming flexibility.

See XOP instruction set for more discussion of compatibility issues between Intel and AMD.

FMA3 instruction set

CPUs with FMA3

Excerpt from FMA3

Supported commands include

Mnemonic Operation Mnemonic Operation
VFMADD result = + a · b + c VFMADDSUB result = a · b + c  for  i = 1, 3, ...
result = a · b − c  for  i = 0, 2, ...
VFNMADD result = − a · b + c
VFMSUB result = + a · b − c VFMSUBADD result = a · b − c  for  i = 1, 3, ...
result = a · b + c  for  i = 0, 2, ...
VFNMSUB result = − a · b − c
Note
  • VFNMADD is  result = − a · b + c, not  result = − (a · b + c).
  • VFNMSUB generates a −0 for all inputs are zero.

Explicit order of operands is included in the mnemonic using numbers "132", "213", and "231":

Postfix
1		 Operation possible
memory operand		 overwrites
 132 a = a · c + b c (factor) a (other factor)
 213 a = b · a + c c (summand) a (factor)
 231 a = b · c + a c (factor) a (summand)

as well as operand format (packed or scalar) and size (single or double).

Postfix
2		 precision size Postfix
2		 precision size
SS Single 00× 32 bit SD Double 0× 64 bit
PSx 04× 32 bit PDx 2× 64 bit
PSy 08× 32 bit PDy 4× 64 bit
PSz 16× 32 bit PDz 8× 64 bit

This results in

Encoding Mnemonic Operands Operation
VEX.256.66.0F38.W1 98 /r VFMADD132PDy ymm, ymm, ymm/m256 a = a · c + b
VEX.256.66.0F38.W0 98 /r VFMADD132PSy
VEX.128.66.0F38.W1 98 /r VFMADD132PDx xmm, xmm, xmm/m128
VEX.128.66.0F38.W0 98 /r VFMADD132PSx
VEX.LIG.66.0F38.W1 99 /r VFMADD132SD xmm, xmm, xmm/m64
VEX.LIG.66.0F38.W0 99 /r VFMADD132SS xmm, xmm, xmm/m32
VEX.256.66.0F38.W1 A8 /r VFMADD213PDy ymm, ymm, ymm/m256 a = b · a + c
VEX.256.66.0F38.W0 A8 /r VFMADD213PSy
VEX.128.66.0F38.W1 A8 /r VFMADD213PDx xmm, xmm, xmm/m128
VEX.128.66.0F38.W0 A8 /r VFMADD213PSx
VEX.LIG.66.0F38.W1 A9 /r VFMADD213SD xmm, xmm, xmm/m64
VEX.LIG.66.0F38.W0 A9 /r VFMADD213SS xmm, xmm, xmm/m32
VEX.256.66.0F38.W1 B8 /r VFMADD231PDy ymm, ymm, ymm/m256 a = b · c + a
VEX.256.66.0F38.W0 B8 /r VFMADD231PSy
VEX.128.66.0F38.W1 B8 /r VFMADD231PDx xmm, xmm, xmm/m128
VEX.128.66.0F38.W0 B8 /r VFMADD231PSx
VEX.LIG.66.0F38.W1 B9 /r VFMADD231SD xmm, xmm, xmm/m64
VEX.LIG.66.0F38.W0 B9 /r VFMADD231SS xmm, xmm, xmm/m32

FMA4 instruction set

CPUs with FMA4

  • AMD
    • "Heavy Equipment" processors
    • Zen: WikiChip's testing shows FMA4 still appears to work (under the conditions of the tests) despite not being officially supported and not even reported by CPUID. This has also been confirmed by Agner.[8] But other tests gave wrong results.[9] AMD Official Web Site FMA4 Support Note ZEN CPUs = AMD ThreadRipper 1900x, R7 Pro 1800, 1700, R5 Pro 1600, 1500, R3 Pro 1300, 1200, R3 2200G, R5 2400G.[10][11][12]
  • Intel
    • Intel has not released CPUs with support for FMA4.

Excerpt from FMA4

Mnemonic (AT&T) Operands Operation
VFMADDPDx xmm, xmm, xmm/m128, xmm/m128 a = b·c + d
VFMADDPDy ymm, ymm, ymm/m256, ymm/m256
VFMADDPSx xmm, xmm, xmm/m128, xmm/m128
VFMADDPSy ymm, ymm, ymm/m256, ymm/m256
VFMADDSD xmm, xmm, xmm/m64, xmm/m64
VFMADDSS xmm, xmm, xmm/m32, xmm/m32

History

The incompatibility between Intel's FMA3 and AMD's FMA4 is due to both companies changing plans without coordinating coding details with each other. AMD changed their plans from FMA3 to FMA4 while Intel changed their plans from FMA4 to FMA3 almost at the same time. The history can be summarized as follows:

  • August 2007: AMD announces the SSE5 instruction set, which includes 3-operand FMA instructions. A new coding scheme (DREX) is introduced for allowing instructions to have three operands.[13]
  • April 2008: Intel announces their AVX and FMA instruction sets, including 4-operand FMA instructions. The coding of these instructions uses the new VEX coding scheme,[14] which is more flexible than AMD's DREX scheme.
  • December 2008: Intel changes the specification for their FMA instructions from 4-operand to 3-operand instructions. The VEX coding scheme is still used.[15]
  • May 2009: AMD changes the specification of their FMA instructions from the 3-operand DREX form to the 4-operand VEX form, compatible with the April 2008 Intel specification rather than the December 2008 Intel specification.[16]
  • October 2011: AMD Bulldozer processor supports FMA4.[17]
  • January 2012: AMD announces FMA3 support in future processors codenamed Trinity and Vishera; they are based on the Piledriver architecture.[18]
  • May 2012: AMD Piledriver processor supports both FMA3 and FMA4.[17]
  • June 2013: Intel Haswell processor supports FMA3.[19]
  • February 2017 The first generation of AMD Ryzen processors officially supports FMA3, but not FMA4 according to the CPUID instruction.[2] There has been confusion regarding whether FMA4 was implemented or not on this processor due to errata in the initial patch to the GNU Binutils package that has since been rectified.[20][21] While the FMA4 instructions seem to work according to some tests, they can also give wrong results.[9] Additionally, the initial Ryzen CPUs could be crashed by a particular sequence of FMA3 instructions. It has since been resolved by an updated CPU microcode.[22]

Compiler and assembler support

Different compilers provide different levels of support for FMA:

References

  1. ^ "FMA3 and FMA4 are not instruction sets, they are individual instructions -- fused multiply add. They could be quite useful depending on how Intel and AMD implement them" Woltmann, George (Prime95). "Intel AVX and GIMPS". mersenneforum.org/index.php. Great Internet Mersenne Prime Search (GIMPS) project. Retrieved 27 July 2011.
  2. ^ a b "The microarchitecture of Intel, AMD and VIA CPUs An optimization guide for assembly programmers and compiler makers" (PDF). Retrieved 2017-05-02.
  3. ^ Maffeo, Robin (March 1, 2012). "AMD and the Visual Studio 11 Beta". AMD. Archived from the original on November 9, 2013. Retrieved 2018-11-07.
  4. ^ "CPU-Z - ID : y5z6gq". Retrieved 2022-05-01.
  5. ^ "CPU-Z - ID : kr2mlx". Retrieved 2022-05-01.
  6. ^ "AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions" (PDF). AMD. May 1, 2009.
  7. ^ "New "Bulldozer" and "Piledriver" Instructions A step forward for high performance software development" (PDF). AMD. October 2012.
  8. ^ "Agner's CPU blog - Test results for AMD Ryzen". 2017-05-02.
  9. ^ a b "Discussion – Ryzen has undocumented support for FMA4". Retrieved 2017-05-10.
  10. ^ "www.amd.com, FMA4 support model list".
  11. ^ "www.amd.com, FMA4 support model list".
  12. ^ "www.amd.com, FMA4 support model list".
  13. ^ . AMD Developer Central. Archived from the original on 2008-01-15. Retrieved 2008-01-28.
  14. ^ "Intel Advanced Vector Extensions Programming Reference" (PDF). Intel. Retrieved 2008-04-05.[permanent dead link]
  15. ^ "Intel Advanced Vector Extensions Programming Reference". Intel. Retrieved 2009-05-06.
  16. ^ "Striking a balance". Dave Christie, AMD Developer blogs. May 6, 2009. Archived from the original on July 8, 2012. Retrieved 2018-11-07.
  17. ^ a b "New Bulldozer and Piledriver Instructions" (PDF). AMD. Retrieved 25 July 2013.
  18. ^ "Software Optimization Guide for AMD Family 15h Processors" (PDF). AMD. Retrieved 19 April 2012.
  19. ^ "Intel Architecture Instruction Set Extensions Programming Reference" (PDF). Intel. Retrieved 25 July 2013.
  20. ^ Gopalasubramanian, Ganesh (2015-03-10). "[PATCH] add znver1 processor". Retrieved 2022-05-01.
  21. ^ Pawar, Amit (2015-08-07). "[PATCH] Remove CpuFMA4 from Znver1 CPU Flags". Retrieved 2022-05-01.
  22. ^ "AMD Ryzen Machine Crashes to a Sequence of FMA3 Instructions". Retrieved 2017-09-10.
  23. ^ a b Latif, Lawrence (Nov 14, 2011). . The Inquirer. Archived from the original on November 17, 2011.{{cite web}}: CS1 maint: unfit URL (link)
  24. ^ "FMA4 Intrinsics Added for Visual Studio 2010 SP1".
  25. ^ . Archived from the original on 2016-06-23. Retrieved 2013-07-24.
  26. ^ "LLVM 3.1 Release Notes".
  27. ^ "Enable detection of AVX and AVX2 support through CPUID". LLVM. 2012-04-26.

January 06, 2023
instruction, wikibooks, book, topic, assembly, avx2, fma3, fma4, extension, streaming, simd, extensions, instructions, microprocessor, instruction, perform, fused, multiply, operations, there, variants, fma4, supported, processors, starting, with, bulldozer, a. Wikibooks has a book on the topic of X86 Assembly AVX AVX2 FMA3 FMA4 The FMA instruction set is an extension to the 128 and 256 bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply add FMA operations 1 There are two variants FMA4 is supported in AMD processors starting with the Bulldozer architecture FMA4 was performed in hardware before FMA3 was Support for FMA4 has been removed since Zen 1 2 FMA3 is supported in AMD processors starting with the Piledriver architecture and Intel starting with Haswell processors and Broadwell processors since 2014 Contents 1 Instructions 2 FMA3 instruction set 2 1 CPUs with FMA3 2 2 Excerpt from FMA3 3 FMA4 instruction set 3 1 CPUs with FMA4 3 2 Excerpt from FMA4 4 History 5 Compiler and assembler support 6 ReferencesInstructions EditFMA3 and FMA4 instructions have almost identical functionality but are not compatible Both contain fused multiply add FMA instructions for floating point scalar and SIMD operations but FMA3 instructions have three operands while FMA4 ones have four The FMA operation has the form d round a b c where the round function performs a rounding to allow the result to fit within the destination register if there are too many significant bits to fit within the destination The four operand form FMA4 allows a b c and d to be four different registers while the three operand form FMA3 requires that d be the same register as a b or c The three operand form makes the code shorter and the hardware implementation slightly simpler while the four operand form provides more programming flexibility See XOP instruction set for more discussion of compatibility issues between Intel and AMD FMA3 instruction set EditCPUs with FMA3 Edit AMD Piledriver 2012 and newer microarchitectures 3 2nd gen APUs Trinity 32nm May 15 2012 2nd gen Bulldozer bdver2 with Piledriver cores October 23 2012 Intel Haswell 2013 and newer processors except Pentiums and Celerons 4 5 Excerpt from FMA3 Edit Supported commands include Mnemonic Operation Mnemonic OperationVFMADD result a b c VFMADDSUB result a b c for i 1 3 result a b c for i 0 2 VFNMADD result a b cVFMSUB result a b c VFMSUBADD result a b c for i 1 3 result a b c for i 0 2 VFNMSUB result a b cNoteVFNMADD is result a b c not result a b c VFNMSUB generates a 0 for all inputs are zero Explicit order of operands is included in the mnemonic using numbers 132 213 and 231 Postfix1 Operation possiblememory operand overwrites 132 a a c b c factor a other factor 213 a b a c c summand a factor 231 a b c a c factor a summand as well as operand format packed or scalar and size single or double Postfix2 precision size Postfix2 precision sizeSS Single 00 32 bit SD Double 0 64 bitPSx 0 4 32 bit PDx 2 64 bitPSy 0 8 32 bit PDy 4 64 bitPSz 16 32 bit PDz 8 64 bitThis results in Encoding Mnemonic Operands OperationVEX 256 66 0F38 W1 98 r VFMADD132PDy ymm ymm ymm m256 a a c bVEX 256 66 0F38 W0 98 r VFMADD132PSyVEX 128 66 0F38 W1 98 r VFMADD132PDx xmm xmm xmm m128VEX 128 66 0F38 W0 98 r VFMADD132PSxVEX LIG 66 0F38 W1 99 r VFMADD132SD xmm xmm xmm m64VEX LIG 66 0F38 W0 99 r VFMADD132SS xmm xmm xmm m32VEX 256 66 0F38 W1 A8 r VFMADD213PDy ymm ymm ymm m256 a b a cVEX 256 66 0F38 W0 A8 r VFMADD213PSyVEX 128 66 0F38 W1 A8 r VFMADD213PDx xmm xmm xmm m128VEX 128 66 0F38 W0 A8 r VFMADD213PSxVEX LIG 66 0F38 W1 A9 r VFMADD213SD xmm xmm xmm m64VEX LIG 66 0F38 W0 A9 r VFMADD213SS xmm xmm xmm m32VEX 256 66 0F38 W1 B8 r VFMADD231PDy ymm ymm ymm m256 a b c aVEX 256 66 0F38 W0 B8 r VFMADD231PSyVEX 128 66 0F38 W1 B8 r VFMADD231PDx xmm xmm xmm m128VEX 128 66 0F38 W0 B8 r VFMADD231PSxVEX LIG 66 0F38 W1 B9 r VFMADD231SD xmm xmm xmm m64VEX LIG 66 0F38 W0 B9 r VFMADD231SS xmm xmm xmm m32FMA4 instruction set EditCPUs with FMA4 Edit AMD Heavy Equipment processors Bulldozer based processors October 12 2011 6 Piledriver based processors 7 Steamroller based processors Excavator based processors including v2 Zen WikiChip s testing shows FMA4 still appears to work under the conditions of the tests despite not being officially supported and not even reported by CPUID This has also been confirmed by Agner 8 But other tests gave wrong results 9 AMD Official Web Site FMA4 Support Note ZEN CPUs AMD ThreadRipper 1900x R7 Pro 1800 1700 R5 Pro 1600 1500 R3 Pro 1300 1200 R3 2200G R5 2400G 10 11 12 Intel Intel has not released CPUs with support for FMA4 Excerpt from FMA4 Edit Mnemonic AT amp T Operands OperationVFMADDPDx xmm xmm xmm m128 xmm m128 a b c dVFMADDPDy ymm ymm ymm m256 ymm m256VFMADDPSx xmm xmm xmm m128 xmm m128VFMADDPSy ymm ymm ymm m256 ymm m256VFMADDSD xmm xmm xmm m64 xmm m64VFMADDSS xmm xmm xmm m32 xmm m32History EditThe incompatibility between Intel s FMA3 and AMD s FMA4 is due to both companies changing plans without coordinating coding details with each other AMD changed their plans from FMA3 to FMA4 while Intel changed their plans from FMA4 to FMA3 almost at the same time The history can be summarized as follows August 2007 AMD announces the SSE5 instruction set which includes 3 operand FMA instructions A new coding scheme DREX is introduced for allowing instructions to have three operands 13 April 2008 Intel announces their AVX and FMA instruction sets including 4 operand FMA instructions The coding of these instructions uses the new VEX coding scheme 14 which is more flexible than AMD s DREX scheme December 2008 Intel changes the specification for their FMA instructions from 4 operand to 3 operand instructions The VEX coding scheme is still used 15 May 2009 AMD changes the specification of their FMA instructions from the 3 operand DREX form to the 4 operand VEX form compatible with the April 2008 Intel specification rather than the December 2008 Intel specification 16 October 2011 AMD Bulldozer processor supports FMA4 17 January 2012 AMD announces FMA3 support in future processors codenamed Trinity and Vishera they are based on the Piledriver architecture 18 May 2012 AMD Piledriver processor supports both FMA3 and FMA4 17 June 2013 Intel Haswell processor supports FMA3 19 February 2017 The first generation of AMD Ryzen processors officially supports FMA3 but not FMA4 according to the CPUID instruction 2 There has been confusion regarding whether FMA4 was implemented or not on this processor due to errata in the initial patch to the GNU Binutils package that has since been rectified 20 21 While the FMA4 instructions seem to work according to some tests they can also give wrong results 9 Additionally the initial Ryzen CPUs could be crashed by a particular sequence of FMA3 instructions It has since been resolved by an updated CPU microcode 22 Compiler and assembler support EditDifferent compilers provide different levels of support for FMA GCC supports FMA4 with mfma4 since version 4 5 0 23 and FMA3 with mfma since version 4 7 0 Microsoft Visual C 2010 SP1 supports FMA4 instructions 24 Microsoft Visual C 2012 supports FMA3 instructions if the processor also supports AVX2 instruction set extension Microsoft Visual C since VC 2013 PathScale supports FMA4 with mfma 25 LLVM 3 1 adds FMA4 support 26 along with preliminary FMA3 support 27 Open64 5 0 adds limited support Intel compilers support only FMA3 instructions 23 NASM supports FMA3 instructions since version 2 03 and FMA4 instructions since 2 06 FASM supports both FMA3 and FMA4 instructions References Edit FMA3 and FMA4 are not instruction sets they are individual instructions fused multiply add They could be quite useful depending on how Intel and AMD implement them Woltmann George Prime95 Intel AVX and GIMPS mersenneforum org index php Great Internet Mersenne Prime Search GIMPS project Retrieved 27 July 2011 a b The microarchitecture of Intel AMD and VIA CPUs An optimization guide for assembly programmers and compiler makers PDF Retrieved 2017 05 02 Maffeo Robin March 1 2012 AMD and the Visual Studio 11 Beta AMD Archived from the original on November 9 2013 Retrieved 2018 11 07 CPU Z ID y5z6gq Retrieved 2022 05 01 CPU Z ID kr2mlx Retrieved 2022 05 01 AMD64 Architecture Programmer s Manual Volume 6 128 Bit and 256 Bit XOP FMA4 and CVT16 Instructions PDF AMD May 1 2009 New Bulldozer and Piledriver Instructions A step forward for high performance software development PDF AMD October 2012 Agner s CPU blog Test results for AMD Ryzen 2017 05 02 a b Discussion Ryzen has undocumented support for FMA4 Retrieved 2017 05 10 www amd com FMA4 support model list www amd com FMA4 support model list www amd com FMA4 support model list 128 Bit SSE5 Instruction Set AMD Developer Central Archived from the original on 2008 01 15 Retrieved 2008 01 28 Intel Advanced Vector Extensions Programming Reference PDF Intel Retrieved 2008 04 05 permanent dead link Intel Advanced Vector Extensions Programming Reference Intel Retrieved 2009 05 06 Striking a balance Dave Christie AMD Developer blogs May 6 2009 Archived from the original on July 8 2012 Retrieved 2018 11 07 a b New Bulldozer and Piledriver Instructions PDF AMD Retrieved 25 July 2013 Software Optimization Guide for AMD Family 15h Processors PDF AMD Retrieved 19 April 2012 Intel Architecture Instruction Set Extensions Programming Reference PDF Intel Retrieved 25 July 2013 Gopalasubramanian Ganesh 2015 03 10 PATCH add znver1 processor Retrieved 2022 05 01 Pawar Amit 2015 08 07 PATCH Remove CpuFMA4 from Znver1 CPU Flags Retrieved 2022 05 01 AMD Ryzen Machine Crashes to a Sequence of FMA3 Instructions Retrieved 2017 09 10 a b Latif Lawrence Nov 14 2011 AMD Bulldozer only FMA4 and XOP instructions are supported by GCC Intel still mute The Inquirer Archived from the original on November 17 2011 a href Template Cite web html title Template Cite web cite web a CS1 maint unfit URL link FMA4 Intrinsics Added for Visual Studio 2010 SP1 EKOPath man doc Archived from the original on 2016 06 23 Retrieved 2013 07 24 LLVM 3 1 Release Notes Enable detection of AVX and AVX2 support through CPUID LLVM 2012 04 26 Retrieved from https en wikipedia org w index php title FMA instruction set amp oldid 1129284492, wikipedia, wiki, book, books, library,

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