In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA, in contrast with third-party DMA where a system DMA controller actually does the transfer.
Some types of buses allow only one device (typically the CPU, or its proxy) to initiate transactions. Most modern bus architectures, such as PCI, allow multiple devices to bus master because it significantly improves performance for general-purpose operating systems. Some real-time operating systems prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency.
While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to main memory.
If multiple devices are able to master the bus, there needs to be a bus arbitration scheme to prevent multiple devices attempting to drive the bus simultaneously. A number of different schemes are used for this; for example SCSI has a fixed priority for each SCSI ID. PCI does not specify the algorithm to use, leaving it up to the implementation to set priorities.
mastering, this, article, includes, list, references, related, reading, external, links, sources, remain, unclear, because, lacks, inline, citations, please, help, improve, this, article, introducing, more, precise, citations, march, 2013, learn, when, remove,. This article includes a list of references related reading or external links but its sources remain unclear because it lacks inline citations Please help improve this article by introducing more precise citations March 2013 Learn how and when to remove this message In computing bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access DMA transactions It is also referred to as first party DMA in contrast with third party DMA where a system DMA controller actually does the transfer Some types of buses allow only one device typically the CPU or its proxy to initiate transactions Most modern bus architectures such as PCI allow multiple devices to bus master because it significantly improves performance for general purpose operating systems Some real time operating systems prohibit peripherals from becoming bus masters because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency While bus mastering theoretically allows one peripheral device to directly communicate with another in practice almost all peripherals master the bus exclusively to perform DMA to main memory If multiple devices are able to master the bus there needs to be a bus arbitration scheme to prevent multiple devices attempting to drive the bus simultaneously A number of different schemes are used for this for example SCSI has a fixed priority for each SCSI ID PCI does not specify the algorithm to use leaving it up to the implementation to set priorities See also editMaster slave technology SCSI initiator and targetReferences editHow Bus Mastering Works Tweak3D What is bus mastering Brevard User s Group nbsp This computer hardware article is a stub You can help Wikipedia by expanding it vte Retrieved from https en wikipedia org w index php title Bus mastering amp oldid 1217838253, wikipedia, wiki, book, books, library,
