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Bit slicing

January 01, 1970

Not to be confused with Bit-banding.
This article is about the processor construction technique. For bit slicing as bit plane separation used in computer graphics and image processing, see Bit plane.

Bit slicing is a technique for constructing a processor from modules of processors of smaller bit width, for the purpose of increasing the word length; in theory to make an arbitrary n-bit central processing unit (CPU). Each of these component modules processes one bit field or "slice" of an operand. The grouped processing components would then have the capability to process the chosen full word-length of a given software design.

Bit slicing more or less died out due to the advent of the microprocessor. Recently it has been used in arithmetic logic units (ALUs) for quantum computers and as a software technique, e.g. for cryptography in x86 CPUs.[1]

Operational details edit

Bit-slice processors (BSPs) usually include 1-, 2-, 4-, 8- or 16-bit arithmetic logic unit (ALU) and control lines (including carry or overflow signals that are internal to the processor in non-bitsliced CPU designs).

For example, two 4-bit ALU chips could be arranged side by side, with control lines between them, to form an 8-bit ALU (result need not be power of two, e.g. three 1-bit units can make a 3-bit ALU,[2] thus 3-bit (or n-bit) CPU, while 3-bit, or any CPU with higher odd number of bits, hasn't been manufactured and sold in volume). Four 4-bit ALU chips could be used to build a 16-bit ALU. It would take eight chips to build a 32-bit word ALU. The designer could add as many slices as required to manipulate longer word lengths.

A microsequencer or control ROM would be used to execute logic to provide data and control signals to regulate function of the component ALUs.

Known bit-slice microprocessors:

  • 2-bit slice:
  • 4-bit slice:
    • National IMP family, consisting primarily of the IMP-00A/520 RALU (also known as MM5750) and various masked ROM microcode and control chips (CROMs, also known as MM5751)
      • National GPC/P / IMP-4 (1973),[5] second-sourced by Rockwell
      • National IMP-8, an 8-bit processor based on the IMP chipset, using two RALU chips and one CROM chip
      • National IMP-16, a 16-bit processor based on the IMP chipset, e.g. four RALU chips with one each IMP16A/521D and IMP16A/522D CROM chips (additional optional CROM chips could provide instruction set additionis)
    • AMD Am2900 family (1975), e.g. AM2901, AM2901A,[6] AM2903[6]
    • Monolithic Memories 5700/6700 family (1974)[7][8][9][10] e.g. MMI 5701 / MMI 6701, second-sourced by ITT Semiconductors
    • Texas Instruments SBP0400 (1975) and SBP0401, cascadable up to 16 bits
    • Texas Instruments SN74181 (1970)
    • Texas Instruments SN74S281 with SN74S282
    • Texas Instruments SN74S481 with SN74S482 (1976)[11]
    • Fairchild 33705[6]
    • Fairchild 9400 (MACROLOGIC), 4700
    • Motorola M10800 family (1979),[12] e.g. MC10800[6]
    • Raytheon RP-16, a 16-bit processor consisting of seven integrated circuits, using four RALU chips and three CROM chips.
  • 8-bit slice:
 
U830C

Historical necessity edit

Bit slicing, although not called that at the time, was also used in computers before large-scale integrated circuits (LSI, the predecessor to today's VLSI, or very-large-scale integration circuits). The first bit-sliced machine was EDSAC 2, built at the University of Cambridge Mathematical Laboratory in 1956–1958.

Prior to the mid-1970s and late 1980s there was some debate over how much bus width was necessary in a given computer system to make it function. Silicon chip technology and parts were much more expensive than today. Using multiple simpler, and thus less expensive, ALUs was seen as a way to increase computing power in a cost-effective manner. While 32-bit microprocessors were being discussed at the time, few were in production.

The UNIVAC 1100 series mainframes (one of the oldest series, originating in the 1950s) has a 36-bit architecture, and the 1100/60 introduced in 1979 used nine Motorola MC10800 4-bit ALU[12] chips to implement the needed word width while using modern integrated circuits.[16]

At the time 16-bit processors were common but expensive, and 8-bit processors, such as the Z80, were widely used in the nascent home-computer market.

Combining components to produce bit-slice products allowed engineers and students to create more powerful and complex computers at a more reasonable cost, using off-the-shelf components that could be custom-configured. The complexities of creating a new computer architecture were greatly reduced when the details of the ALU were already specified (and debugged).

The main advantage was that bit slicing made it economically possible in smaller processors to use bipolar transistors, which switch much faster than NMOS or CMOS transistors. This allowed much higher clock rates, where speed was needed – for example, for DSP functions or matrix transformation – or, as in the Xerox Alto, the combination of flexibility and speed, before discrete CPUs were able to deliver that.

Modern use edit

Software use on non-bit-slice hardware edit

In more recent times, the term bit slicing was reused by Matthew Kwan[17] to refer to the technique of using a general-purpose CPU to implement multiple parallel simple virtual machines using general logic instructions to perform single-instruction multiple-data (SIMD) operations. This technique is also known as SIMD within a register (SWAR).

This was initially in reference to Eli Biham's 1997 article A Fast New DES Implementation in Software,[18] which achieved significant gains in performance of DES by using this method.

Bit-sliced quantum computers edit

To simplify the circuit structure and reduce the hardware cost of quantum computers (proposed to run the MIPS32 instruction set) a 50 GHz superconducting "4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated".[19]

See also edit

References edit

  1. ^ Benadjila, Ryad; Guo, Jian; Lomné, Victor; Peyrin, Thomas (2014-03-21) [2013-07-15]. "Implementing Lightweight Block Ciphers on x86 Architectures". Cryptology Archive. Report 2013/445. from the original on 2017-08-17. Retrieved 2019-12-28.
  2. ^ . www.cs.umd.edu. Archived from the original on 2017-05-08. […] Here's how you would put three 1-bit ALU to create a 3-bit ALU […]
  3. ^ "3002 - The CPU Shack Museum". cpushack.com. Retrieved 2017-11-05.
  4. ^ "Technology Leadership - Bipolar Microprocessor" (PDF). Signetics. S2.95. Retrieved 2021-10-11.
  5. ^ "IMP-4 - National Semiconductor". en.wikichip.org. Retrieved 2017-11-05.
  6. ^ a b c d e Klar, Rainer (1989) [1988-10-01]. "5.2 Der Mikroprozessor, ein Universal-Rechenautomat". Digitale Rechenautomaten – Eine Einführung in die Struktur von Computerhardware [Digital Computers – An Introduction into the structure of computer hardware]. Sammlung Göschen (in German). Vol. 2050 (4th reworked ed.). Berlin, Germany: Walter de Gruyter & Co. p. 198. ISBN 3-11011700-2. (320 pages)
  7. ^ "6701 - The CPU Shack Museum". cpushack.com. Retrieved 2017-11-05.
  8. ^ "5700/6700 - Monolithic Memories". en.wikichip.org. Retrieved 2017-11-05.
  9. ^ "File:MMI 5701-6701 MCU (August, 1974).pdf" (PDF). en.wikichip.org. Retrieved 2017-11-05.
  10. ^ "5701/6701 4-Bit Expandable Bipolar Microcontroller Aug74" (PDF). Retrieved 2021-05-24.
  11. ^ "SN74S481". The CPU Shack Museum. Retrieved 2017-11-05.
  12. ^ a b Mueller, Dieter (2012). "The MC10800". 6502.org. from the original on 2018-07-18. Retrieved 2017-11-05.
  13. ^ Kurth, Rüdiger; Groß, Martin; Hunger, Henry, eds. (2021-09-27) [2006]. "Integrierte Schaltkreise" [Integrated Circuits]. robotrontechnik.de (in German). from the original on 2021-12-03. Retrieved 2021-12-07.
  14. ^ Oppelt, Dirk (2016). "Eastern Bloc DEC PDP". cpu-collection.de. Nuremberg, Germany. from the original on 2016-08-09. Retrieved 2021-12-07.
  15. ^ Salomon, Peter (2007-06-25). "Einsatzgebiete des U830C und Chipsatz" [Applications of the U830C and chipset]. Robotrontechnik-Forum (in German). from the original on 2019-11-10. Retrieved 2021-12-07.
  16. ^ "Computers Sperry Univac 1100/60 System" (PDF). Delran, NJ, USA: Datapro Research Corporation. January 1983. 70C-877-12. Retrieved 2021-10-11.
  17. ^ "Bitslice DES". darkside.com.au. Retrieved 2017-11-05.
  18. ^ Biham, Eli (1997). "A Fast New DES Implementation in Software". cs.technion.ac.il. Retrieved 2017-11-05.
  19. ^ Tang, Guang-Ming; Takata, Kensuke; Tanaka, Masamitsu; Fujimaki, Akira; Takagi, Kazuyoshi; Takagi, Naofumi (January 2016) [2015-12-09]. "4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors". IEEE Transactions on Applied Superconductivity. 26 (1): 2507125. Bibcode:2016ITAS...2607125T. doi:10.1109/TASC.2015.2507125. S2CID 25478156. 1300106. […] 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. […] It consists of 3481 Josephson junctions with an area of 3.09 × 1.66 mm2. It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV […] Another 8-bit parallel ALU has been designed and fabricated with target processing frequency of 30 GHz […] To achieve comparable performance to CMOS parallel microprocessors operating at 2–3 GHz, 4-bit bit-slice processing should be performed with a clock frequency of several tens of gigahertz. Several bit-serial arithmetic circuits have been successfully demonstrated with high-speed clocks of above 50 GHz […]

Further reading edit

  • Mick, John; Brick, James (1980). Bit-Slice Microprocessor Design (PDF). McGraw-Hill. ISBN 0-07-041781-4.

External links edit

January 01, 1970
slicing, confused, with, banding, this, article, about, processor, construction, technique, slicing, plane, separation, used, computer, graphics, image, processing, plane, help, expand, this, article, with, text, translated, from, corresponding, article, russi. Not to be confused with Bit banding This article is about the processor construction technique For bit slicing as bit plane separation used in computer graphics and image processing see Bit plane You can help expand this article with text translated from the corresponding article in Russian May 2017 Click show for important translation instructions Machine translation like DeepL or Google Translate is a useful starting point for translations but translators must revise errors as necessary and confirm that the translation is accurate rather than simply copy pasting machine translated text into the English Wikipedia Do not translate text that appears unreliable or low quality If possible verify the text with references provided in the foreign language article You must provide copyright attribution in the edit summary accompanying your translation by providing an interlanguage link to the source of your translation A model attribution edit summary is Content in this edit is translated from the existing Russian Wikipedia article at ru Mikroprocessornaya sekciya see its history for attribution You may also add the template Translated ru Mikroprocessornaya sekciya to the talk page For more guidance see Wikipedia Translation This article relies excessively on references to primary sources Please improve this article by adding secondary or tertiary sources Find sources Bit slicing news newspapers books scholar JSTOR January 2014 Learn how and when to remove this message Bit slicing is a technique for constructing a processor from modules of processors of smaller bit width for the purpose of increasing the word length in theory to make an arbitrary n bit central processing unit CPU Each of these component modules processes one bit field or slice of an operand The grouped processing components would then have the capability to process the chosen full word length of a given software design Bit slicing more or less died out due to the advent of the microprocessor Recently it has been used in arithmetic logic units ALUs for quantum computers and as a software technique e g for cryptography in x86 CPUs 1 Contents 1 Operational details 2 Historical necessity 3 Modern use 3 1 Software use on non bit slice hardware 3 2 Bit sliced quantum computers 4 See also 5 References 6 Further reading 7 External linksOperational details editBit slice processors BSPs usually include 1 2 4 8 or 16 bit arithmetic logic unit ALU and control lines including carry or overflow signals that are internal to the processor in non bitsliced CPU designs For example two 4 bit ALU chips could be arranged side by side with control lines between them to form an 8 bit ALU result need not be power of two e g three 1 bit units can make a 3 bit ALU 2 thus 3 bit or n bit CPU while 3 bit or any CPU with higher odd number of bits hasn t been manufactured and sold in volume Four 4 bit ALU chips could be used to build a 16 bit ALU It would take eight chips to build a 32 bit word ALU The designer could add as many slices as required to manipulate longer word lengths A microsequencer or control ROM would be used to execute logic to provide data and control signals to regulate function of the component ALUs Known bit slice microprocessors 2 bit slice Intel 3000 family 1974 now discontinued e g Intel 3002 with Intel 3001 second sourced by Signetics and Intersil 3 Signetics 8X02 family 1977 now discontinued 4 4 bit slice National IMP family consisting primarily of the IMP 00A 520 RALU also known as MM5750 and various masked ROM microcode and control chips CROMs also known as MM5751 National GPC P IMP 4 1973 5 second sourced by Rockwell National IMP 8 an 8 bit processor based on the IMP chipset using two RALU chips and one CROM chip National IMP 16 a 16 bit processor based on the IMP chipset e g four RALU chips with one each IMP16A 521D and IMP16A 522D CROM chips additional optional CROM chips could provide instruction set additionis AMD Am2900 family 1975 e g AM2901 AM2901A 6 AM2903 6 Monolithic Memories 5700 6700 family 1974 7 8 9 10 e g MMI 5701 MMI 6701 second sourced by ITT Semiconductors Texas Instruments SBP0400 1975 and SBP0401 cascadable up to 16 bits Texas Instruments SN74181 1970 Texas Instruments SN74S281 with SN74S282 Texas Instruments SN74S481 with SN74S482 1976 11 Fairchild 33705 6 Fairchild 9400 MACROLOGIC 4700 Motorola M10800 family 1979 12 e g MC10800 6 Raytheon RP 16 a 16 bit processor consisting of seven integrated circuits using four RALU chips and three CROM chips 8 bit slice nbsp U830C Four Phase Systems AL1 1969 considered to be the first microprocessor used in a commercial product now discontinued Texas Instruments SN54AS888 SN74AS888 Fairchild 100K 6 ZMD U830C de 13 14 15 1978 1981 cascadable up to 32 bit 16 bit slice AMD Am29100 family Synopsys 49C402 ZFT Robotron ZFTM Dresden U840 de 1979 1982 unreleasedHistorical necessity editBit slicing although not called that at the time was also used in computers before large scale integrated circuits LSI the predecessor to today s VLSI or very large scale integration circuits The first bit sliced machine was EDSAC 2 built at the University of Cambridge Mathematical Laboratory in 1956 1958 Prior to the mid 1970s and late 1980s there was some debate over how much bus width was necessary in a given computer system to make it function Silicon chip technology and parts were much more expensive than today Using multiple simpler and thus less expensive ALUs was seen as a way to increase computing power in a cost effective manner While 32 bit microprocessors were being discussed at the time few were in production The UNIVAC 1100 series mainframes one of the oldest series originating in the 1950s has a 36 bit architecture and the 1100 60 introduced in 1979 used nine Motorola MC10800 4 bit ALU 12 chips to implement the needed word width while using modern integrated circuits 16 At the time 16 bit processors were common but expensive and 8 bit processors such as the Z80 were widely used in the nascent home computer market Combining components to produce bit slice products allowed engineers and students to create more powerful and complex computers at a more reasonable cost using off the shelf components that could be custom configured The complexities of creating a new computer architecture were greatly reduced when the details of the ALU were already specified and debugged The main advantage was that bit slicing made it economically possible in smaller processors to use bipolar transistors which switch much faster than NMOS or CMOS transistors This allowed much higher clock rates where speed was needed for example for DSP functions or matrix transformation or as in the Xerox Alto the combination of flexibility and speed before discrete CPUs were able to deliver that Modern use editSoftware use on non bit slice hardware edit In more recent times the term bit slicing was reused by Matthew Kwan 17 to refer to the technique of using a general purpose CPU to implement multiple parallel simple virtual machines using general logic instructions to perform single instruction multiple data SIMD operations This technique is also known as SIMD within a register SWAR This was initially in reference to Eli Biham s 1997 article A Fast New DES Implementation in Software 18 which achieved significant gains in performance of DES by using this method Bit sliced quantum computers edit To simplify the circuit structure and reduce the hardware cost of quantum computers proposed to run the MIPS32 instruction set a 50 GHz superconducting 4 bit bit slice arithmetic logic unit ALU for 32 bit rapid single flux quantum microprocessors was demonstrated 19 See also editBit serial architectureReferences edit Benadjila Ryad Guo Jian Lomne Victor Peyrin Thomas 2014 03 21 2013 07 15 Implementing Lightweight Block Ciphers on x86 Architectures Cryptology Archive Report 2013 445 Archived from the original on 2017 08 17 Retrieved 2019 12 28 How to Create a 1 bit ALU www cs umd edu Archived from the original on 2017 05 08 Here s how you would put three 1 bit ALU to create a 3 bit ALU 3002 The CPU Shack Museum cpushack com Retrieved 2017 11 05 Technology Leadership Bipolar Microprocessor PDF Signetics S2 95 Retrieved 2021 10 11 IMP 4 National Semiconductor en wikichip org Retrieved 2017 11 05 a b c d e Klar Rainer 1989 1988 10 01 5 2 Der Mikroprozessor ein Universal Rechenautomat Digitale Rechenautomaten Eine Einfuhrung in die Struktur von Computerhardware Digital Computers An Introduction into the structure of computer hardware Sammlung Goschen in German Vol 2050 4th reworked ed Berlin Germany Walter de Gruyter amp Co p 198 ISBN 3 11011700 2 320 pages 6701 The CPU Shack Museum cpushack com Retrieved 2017 11 05 5700 6700 Monolithic Memories en wikichip org Retrieved 2017 11 05 File MMI 5701 6701 MCU August 1974 pdf PDF en wikichip org Retrieved 2017 11 05 5701 6701 4 Bit Expandable Bipolar Microcontroller Aug74 PDF Retrieved 2021 05 24 SN74S481 The CPU Shack Museum Retrieved 2017 11 05 a b Mueller Dieter 2012 The MC10800 6502 org Archived from the original on 2018 07 18 Retrieved 2017 11 05 Kurth Rudiger Gross Martin Hunger Henry eds 2021 09 27 2006 Integrierte Schaltkreise Integrated Circuits robotrontechnik de in German Archived from the original on 2021 12 03 Retrieved 2021 12 07 Oppelt Dirk 2016 Eastern Bloc DEC PDP cpu collection de Nuremberg Germany Archived from the original on 2016 08 09 Retrieved 2021 12 07 Salomon Peter 2007 06 25 Einsatzgebiete des U830C und Chipsatz Applications of the U830C and chipset Robotrontechnik Forum in German Archived from the original on 2019 11 10 Retrieved 2021 12 07 Computers Sperry Univac 1100 60 System PDF Delran NJ USA Datapro Research Corporation January 1983 70C 877 12 Retrieved 2021 10 11 Bitslice DES darkside com au Retrieved 2017 11 05 Biham Eli 1997 A Fast New DES Implementation in Software cs technion ac il Retrieved 2017 11 05 Tang Guang Ming Takata Kensuke Tanaka Masamitsu Fujimaki Akira Takagi Kazuyoshi Takagi Naofumi January 2016 2015 12 09 4 bit Bit Slice Arithmetic Logic Unit for 32 bit RSFQ Microprocessors IEEE Transactions on Applied Superconductivity 26 1 2507125 Bibcode 2016ITAS 2607125T doi 10 1109 TASC 2015 2507125 S2CID 25478156 1300106 4 bit bit slice arithmetic logic unit ALU for 32 bit rapid single flux quantum microprocessors was demonstrated The proposed ALU covers all of the ALU operations for the MIPS32 instruction set It consists of 3481 Josephson junctions with an area of 3 09 1 66 mm2 It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32 bit operation at the designed DC bias voltage of 2 5 mV Another 8 bit parallel ALU has been designed and fabricated with target processing frequency of 30 GHz To achieve comparable performance to CMOS parallel microprocessors operating at 2 3 GHz 4 bit bit slice processing should be performed with a clock frequency of several tens of gigahertz Several bit serial arithmetic circuits have been successfully demonstrated with high speed clocks of above 50 GHz Further reading editMick John Brick James 1980 Bit Slice Microprocessor Design PDF McGraw Hill ISBN 0 07 041781 4 External links edit Untwisted Bit sliced TEA time Archived from the original on 2013 10 21 a bitslicing primer presenting a pedagogical bitsliced implementation of the Tiny Encryption Algorithm TEA a block cipher Retrieved from https en wikipedia org w index php title Bit slicing amp oldid 1221399827, wikipedia, wiki, book, books, library,

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