Aldec was founded in 1984 by Dr. Stanley M. Hyduke.
In 1985 the company released its first product: MS-DOS-based gate-level simulator SUSIE. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCAD.
Sensing growing popularity of Microsoft Windows, ALDEC ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as Active-CAD (some low-end versions of the suite were for some time sold under Susie-CAD brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit.
In 1996 Aldec signed agreement with Xilinx that allowed distribution of Xilinx-only version of Active-CAD under the Foundation name.
While VHDL and Verilog were supported by Active-CAD in the form of schematic macros, the release of Active-VHDL in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to Active-HDL and is still available (as of 2020).
In 2000 ALDEC released high-performance HDL simulator working not only on Windows, but also on Solaris and Linux platforms.[2]
In 2001 ALDEC added hardware to its product line: HES (Hardware Embedded Simulation) Platform that allows hardware acceleration of HDL simulation and incremental prototyping of hardware.
Year 2003 marks the release of Riviera-PRO supporting assertion based verification (OpenVera, PSL and SystemVerilog can be used to write properties, assertions and coverage.)
Support for SystemC and non-assertion part of SystemVerilog was added in 2004. Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005.
In 2006 Riviera-PRO was the first simulator supporting Open IP Encryption Initiative by Synplicity.[3]
Stimulated by requests from Verilog users, ALDEC released in 2007 an advanced, user-configurable lint tool implementing rules created by - Japanese consortium of major silicon vendors.
In 2008, releases ALINT: Design Rule Checker (STARC – Japanese Consortium of 11 ASIC Companies)
2010, releases Support for VHDL IEEE 1076-2008.
In 2010, Aldec's Active-HDL wins Best FPGA Design & Simulation Tool in China
In 2011, Aldec delivers UVM 1.0, OVM 2.1.2 & VMM 1.1.1a Support, releases 4 MHz Design Emulator, and wins Best FPGA Design & Verification Platform Provider in China.
In 2012, Aldec enters SoC/ASIC Prototyping Market with HES-7 and jointly launches OSVVM, VHDL Verification.
In 2013, Aldec releases Spec-TRACER Requirements Lifecycle Management
In 2015, Aldec Releases ALINT-PRO with CDC Verification.
In 2016, Aldec releases TySOM Product Line for Embedded Development using SoC FPGAs
In 2020, Releases Support for VHDL IEEE 1076-2019.
Products
Software
Active-HDL - FPGA development environment built around common kernel HDL simulator. Supports text-based and graphical design entry and debugging tools, allows mixed-language simulation (VHDL/Verilog/EDIF/SystemC/SystemVerilog) and provides unified interface to various synthesis and implementation tools. Also supports assertion based verification with Open Vera, PSL, or Systemverilog Assertion statements. Special versions of the software that support just one FPGA vendor are available, e.g. Active-HDL Lattice Edition. Only available on MS Windows platform.
Riviera-PRO - high-end HDL simulator targeting ASIC and large FPGA designs. Riviera-PRO extends Active-HDL's simulation features with support for advanced verification methodologies such as linting, functional coverage, OVM and UVM, hardware acceleration, and prototyping. Riviera-PRO is a new generation of the tool known as Riviera-Classic and is available in 32-bit and 64-bit on MS Windows and Linux.
HES-DVM - solution allowing acceleration of HDL simulation (10x to 50x verification time reduction), emulation of the entire design and hardware/software co-simulation (useful in Embedded System development).
ALINT-PRO - single framework for design rule checker/linting and CDC analysis. ALINT-PRO is able to conduct extensive textual analysis of individual Verilog, VHDL and SystemVerilog design sources and advanced checks of the entire design hierarchy. Multiple sets of highly configurable, predefined rules are available and new, custom rules can be created using provided API. Built-in Phase-Based Linting methodology allows faster, more efficient checking of rules. ALINT-PRO smoothly supports running the rule checks for designs that target FPGA implementation using Xilinx, Intel, Microsemi, and Lattice technologies with minimal setup
Spec-TRACER - unified requirements life-cycle management application designed specifically for FPGA and ASIC designs. Facilitates requirements capture, management, analysis, traceability and reporting; integrates with Windows-based HDL design and simulation tools.
IP Products - a set of general-purpose Intellectual Property blocks created by Aldec and its partners, validated in Active-HDL and Riviera-PRO environments.
Hardware
HES-7 - high capacity, high density, FPGA-based ASIC prototyping solution. With help of Xilinx Virtex-7 FPGA-based prototyping boards, HES-7 allows testing designs of up to 24 million ASIC gates.
Microsemi RTAX/RTSX Prototyping - the efficient way of prototyping designs with radiation hardened FPGA by using footprint-compatible prototyping boards with flash-based, reprogrammable chips on top. The solution includes optional software for netlist translation.
DO-254 Compliance Test System (CTS) - It is a complete verification solution that can assure the FPGA on your system to be DO-254/ED80 compliant. The CTS gives the user the ability to perform an advanced way of In-Hardware Simulation instead of the traditional Hardware Testing. As test vectors for the In-Hardware Simulation, you can reuse the same testbench with 100% Code Coverage results captured from RTL simulation. By reusing the same testbench, the Hardware Verification can easily achieve requirements traceability. You can perform the In-Hardware Simulation at speed at the target device. The CTS also allows easy comparison and debugging of the In-Hardware Simulation and HDL Simulation results via waveform format.
TySOM - Embedded development boards and FMC daughter cards based on Xilinx Zynq-7000 series targeting IoT, ADAS and Industrial Machine Vision.
Education
Aldec provides fully functional, heavily discounted versions of its software for educational institutions worldwide (Kumaon Engineering College, ).
Aldec also offers a special Student-Edition of Active-HDL, downloadable from Aldec's website. The Student-Edition has limited design capacity and some reduction of program functionality, but supports both design languages (Verilog resp. VHDL).
The company also supports local education - in 1999 it contributed to the establishment of the "Aldec Digital Design Laboratory" at the UNLV.[4]
Aldec software is packaged with several electronic design related books (e.g. "Digital Design: Principles and Practices", "CONTEMPORARY LOGIC DESIGN").
Student Edition of Active-HDL was the first HDL simulator to be sold at Walmart.[5]
^EN-genius Programmable logic ZONE, "Lattice And Aldec Form Alliance For FPGA Design And Design Verification"
^Richard Goering, "Aldec rolls out Linux-based mixed-language simulator", EETimes.com, November 13, 2000
^Christine Evans-Pughe, "Protecting your IP just got simpler" 2006-10-18 at the Wayback Machine, Paragraph 11, Electronics Weekly, October 13, 2006
^ECE-UNLV staff, "ALDEC, (...) plays a significant role in ECE programs" 2006-07-20 at the Wayback Machine, Page 3, ECE-UNLV News, Vol 5, 2005
^EDN Online Staff, "EDA Software Sold in Walmart." 2007-09-27 at the Wayback Machine, EDN, February 20, 2006
External links
Official site
February 05, 2023
aldec, privately, owned, electronic, design, automation, company, based, henderson, nevada, that, provides, software, hardware, used, creation, verification, digital, designs, targeting, fpga, asic, technologies, aldec, typeprivateindustryedafounded1984headqua. Aldec Inc is a privately owned electronic design automation company based in Henderson Nevada that provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies ALDEC Inc TypePrivateIndustryEDAFounded1984HeadquartersHenderson Nevada United StatesProductsActive HDL ALINT PRO Riviera PRO Spec TRACER RTAX RTSX Prototyping HES DVM HES 7 TySOMWebsitealdec comAs a member of Accellera and IEEE Standards Association Aldec actively participates in the process of developing new standards and updating existing standards e g VHDL SystemVerilog Aldec provides a hardware description language HDL simulation engine for other EDA tools such as Altium Designer and bundles special version of its tools with FPGA vendors software such as Lattice 1 Contents 1 History 2 Products 2 1 Software 2 2 Hardware 3 Education 4 See also 5 References 6 External linksHistory EditAldec was founded in 1984 by Dr Stanley M Hyduke In 1985 the company released its first product MS DOS based gate level simulator SUSIE For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCAD Sensing growing popularity of Microsoft Windows ALDEC ported its simulator to this platform and added schematic entry and design management tool The new software suite was released in 1992 as Active CAD some low end versions of the suite were for some time sold under Susie CAD brand One of the distinguishing features of Active CAD was the ability of instantaneous transfer of schematic changes to the simulator allowing quick verification of the behavior of the modified circuit In 1996 Aldec signed agreement with Xilinx that allowed distribution of Xilinx only version of Active CAD under the Foundation name While VHDL and Verilog were supported by Active CAD in the form of schematic macros the release of Active VHDL in 1997 marked the shift from netlist based design to HDL based design After adding Verilog support Active VHDL was renamed to Active HDL and is still available as of 2020 In 2000 ALDEC released high performance HDL simulator working not only on Windows but also on Solaris and Linux platforms 2 In 2001 ALDEC added hardware to its product line HES Hardware Embedded Simulation Platform that allows hardware acceleration of HDL simulation and incremental prototyping of hardware Year 2003 marks the release of Riviera PRO supporting assertion based verification OpenVera PSL and SystemVerilog can be used to write properties assertions and coverage Support for SystemC and non assertion part of SystemVerilog was added in 2004 Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005 In 2006 Riviera PRO was the first simulator supporting Open IP Encryption Initiative by Synplicity 3 Stimulated by requests from Verilog users ALDEC released in 2007 an advanced user configurable lint tool implementing rules created by STARC Japanese consortium of major silicon vendors In 2008 releases ALINT Design Rule Checker STARC Japanese Consortium of 11 ASIC Companies 2010 releases Support for VHDL IEEE 1076 2008 In 2010 Aldec s Active HDL wins Best FPGA Design amp Simulation Tool in China In 2011 Aldec delivers UVM 1 0 OVM 2 1 2 amp VMM 1 1 1a Support releases 4 MHz Design Emulator and wins Best FPGA Design amp Verification Platform Provider in China In 2012 Aldec enters SoC ASIC Prototyping Market with HES 7 and jointly launches OSVVM VHDL Verification In 2013 Aldec releases Spec TRACER Requirements Lifecycle Management In 2015 Aldec Releases ALINT PRO with CDC Verification In 2016 Aldec releases TySOM Product Line for Embedded Development using SoC FPGAs In 2020 Releases Support for VHDL IEEE 1076 2019 Products EditSoftware Edit Active HDL FPGA development environment built around common kernel HDL simulator Supports text based and graphical design entry and debugging tools allows mixed language simulation VHDL Verilog EDIF SystemC SystemVerilog and provides unified interface to various synthesis and implementation tools Also supports assertion based verification with Open Vera PSL or Systemverilog Assertion statements Special versions of the software that support just one FPGA vendor are available e g Active HDL Lattice Edition Only available on MS Windows platform Riviera PRO high end HDL simulator targeting ASIC and large FPGA designs Riviera PRO extends Active HDL s simulation features with support for advanced verification methodologies such as linting functional coverage OVM and UVM hardware acceleration and prototyping Riviera PRO is a new generation of the tool known as Riviera Classic and is available in 32 bit and 64 bit on MS Windows and Linux HES DVM solution allowing acceleration of HDL simulation 10x to 50x verification time reduction emulation of the entire design and hardware software co simulation useful in Embedded System development ALINT PRO single framework for design rule checker linting and CDC analysis ALINT PRO is able to conduct extensive textual analysis of individual Verilog VHDL and SystemVerilog design sources and advanced checks of the entire design hierarchy Multiple sets of highly configurable predefined rules are available and new custom rules can be created using provided API Built in Phase Based Linting methodology allows faster more efficient checking of rules ALINT PRO smoothly supports running the rule checks for designs that target FPGA implementation using Xilinx Intel Microsemi and Lattice technologies with minimal setup Spec TRACER unified requirements life cycle management application designed specifically for FPGA and ASIC designs Facilitates requirements capture management analysis traceability and reporting integrates with Windows based HDL design and simulation tools IP Products a set of general purpose Intellectual Property blocks created by Aldec and its partners validated in Active HDL and Riviera PRO environments Hardware Edit HES 7 high capacity high density FPGA based ASIC prototyping solution With help of Xilinx Virtex 7 FPGA based prototyping boards HES 7 allows testing designs of up to 24 million ASIC gates Microsemi RTAX RTSX Prototyping the efficient way of prototyping designs with radiation hardened FPGA by using footprint compatible prototyping boards with flash based reprogrammable chips on top The solution includes optional software for netlist translation DO 254 Compliance Test System CTS It is a complete verification solution that can assure the FPGA on your system to be DO 254 ED80 compliant The CTS gives the user the ability to perform an advanced way of In Hardware Simulation instead of the traditional Hardware Testing As test vectors for the In Hardware Simulation you can reuse the same testbench with 100 Code Coverage results captured from RTL simulation By reusing the same testbench the Hardware Verification can easily achieve requirements traceability You can perform the In Hardware Simulation at speed at the target device The CTS also allows easy comparison and debugging of the In Hardware Simulation and HDL Simulation results via waveform format TySOM Embedded development boards and FMC daughter cards based on Xilinx Zynq 7000 series targeting IoT ADAS and Industrial Machine Vision Education EditAldec provides fully functional heavily discounted versions of its software for educational institutions worldwide Kumaon Engineering College National Technology University Aldec also offers a special Student Edition of Active HDL downloadable from Aldec s website The Student Edition has limited design capacity and some reduction of program functionality but supports both design languages Verilog resp VHDL The company also supports local education in 1999 it contributed to the establishment of the Aldec Digital Design Laboratory at the UNLV 4 Aldec software is packaged with several electronic design related books e g Digital Design Principles and Practices CONTEMPORARY LOGIC DESIGN Student Edition of Active HDL was the first HDL simulator to be sold at Walmart 5 See also EditVHDL Verilog SystemVerilog SystemCReferences Edit EN genius Programmable logic ZONE Lattice And Aldec Form Alliance For FPGA Design And Design Verification Richard Goering Aldec rolls out Linux based mixed language simulator EETimes com November 13 2000 Christine Evans Pughe Protecting your IP just got simpler Archived 2006 10 18 at the Wayback Machine Paragraph 11 Electronics Weekly October 13 2006 ECE UNLV staff ALDEC plays a significant role in ECE programs Archived 2006 07 20 at the Wayback Machine Page 3 ECE UNLV News Vol 5 2005 EDN Online Staff EDA Software Sold in Walmart Archived 2007 09 27 at the Wayback Machine EDN February 20 2006External links EditOfficial site Retrieved from https en wikipedia org w index php title Aldec amp oldid 1061653464, wikipedia, wiki, book, books, library,
