SPARC T5 is the fifth generation multicore microprocessor of Oracle'sSPARC T series family.[1] It was first presented at Hot Chips 24 in August 2012,[2] and was officially introduced with the Oracle SPARC T5 servers in March 2013.[3] The processor is designed to offer high multithreaded performance (16 cores per chip, with 8 threads per core), as well as high single threaded performance from the same chip.[4]
The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz.[5] The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution,[6] incorporates one floating point unit, one dedicated cryptographic unit per core.[7]
The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8 socket system.[4] Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.[5]
The SPARC T5 also introduces a new power management feature that consists of hardware support in the processor, and the software that allows system administrator to use the feature. Users select the policy how the system responds to over-temperature and over-current events. The dynamic voltage and frequency scaling (aka DVFS) policy can be set to maintain peak frequency, or to trade off between performance and power consumption.[5]
SPARC T5 in systemsedit
The SPARC T5 processor is used in Oracle's entry and mid-size SPARC T5-2, T5-4, and T5-8 servers. All servers use the same processor frequency, number of cores per chip and cache configuration.[12]
The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache. Multiprocessor cache coherence is maintained using a directory-based protocol.[5] The design scales up to eight sockets without additional silicon (glueless). The snooping based protocol used in SPARC T4 systems was replaced in order to reduce memory latency and reduce coherency bandwidth consumption.[5][13]
Referencesedit
^"High-Performance Security for Oracle WebLogic server Applications Using Oracle's SPARC T5 and SPARC M5 Servers, White Paper" (PDF), www.oracle.com, Oracle Corporation, May 2012
^Timothy Prickett Morgan (4 September 2012), "Oracle hurls Sparc T5 gladiators into big-iron arena", www.theregister.co.uk, The Register
^Timothy Prickett Morgan (26 March 2013), "Oracle's new T5 Sparcs boost scalability in chip and chassis", www.theregister.co.uk, The Register
^ abc"SPARC T4 Processor Data Sheet" (PDF), www.oracle.com, Oracle Corporation
^ abcdeJohn Feehrer; Sumti Jairath; Paul Loewenstein; Ram Sivaramakrishnan; David Smentek; Sebastian Turullols; Ali Vahidsafa (March–April 2013), IEEE Micro, vol. 33, no. 2, The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets, pp. 48-57, IEEE Computer Society, ISSN 0272-1732
^"SPARC T5 Processor Data Sheet" (PDF), www.oracle.com, Oracle Corporation
^Manish Shah; Robert Golla; Gregory Grohoski; Paul Jordan; Jama Barreh; Jeff Brooks; Mark Greenberg; Gideon Levinsky; Mark Luttrell; Christopher Olson; Zeid Samoail; Matt Smittle; Tom Ziaja (March–April 2012), IEEE Micro, vol. 32, no. 2, Sparc T4: A Dynamically Threaded Server-on-a-Chip, pp. 8-19, IEEE Computer Society
^Oracle SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture(PDF), Oracle Corporation
^"Oracle SPARC T7 and SPARC M7 Server Architecture" (PDF), www.oracle.com, Oracle Corporation
^ ab"Oracle SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture, An Oracle White Paper, p. 28" (PDF), www.oracle.com, Oracle Corporation, June 2012
^ ab"Oracle SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture, An Oracle White Paper, p. 29" (PDF), www.oracle.com, Oracle Corporation, February 2014
^Jean Bozman (April 5, 2013), Oracle Launches T5 and M5 Servers: A New Generation of Oracle's SPARC/Solaris Servers, IDC, ISSN 0272-1732
^"SPARC T5 Deep Dive: An interview with Oracle's Rick Hetherington", www.oracle.com, Oracle Corporation
External linksedit
April 30, 2024
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This article relies excessively on references to primary sources Please improve this article by adding secondary or tertiary sources Find sources SPARC T5 news newspapers books scholar JSTOR July 2013 Learn how and when to remove this message SPARC T5 is the fifth generation multicore microprocessor of Oracle s SPARC T series family 1 It was first presented at Hot Chips 24 in August 2012 2 and was officially introduced with the Oracle SPARC T5 servers in March 2013 3 The processor is designed to offer high multithreaded performance 16 cores per chip with 8 threads per core as well as high single threaded performance from the same chip 4 SPARC T5Oracle SPARC T5General informationLaunched2013Discontinued2017PerformanceMax CPU clock rate3 6 GHzCacheL1 cache16 16 16 KBL2 cache16 128 KBL3 cache8 MBArchitecture and classificationTechnology node28 nmInstruction setSPARC V9Physical specificationsCores16Products models variantsCore name s S3HistoryPredecessor s SPARC T4Successor s SPARC M7 The processor uses the same SPARC S3 core design as its predecessor the SPARC T4 processor but is implemented in a 28 nm process and runs at 3 6 GHz 5 The S3 core is a dual issue core that uses dynamic threading and out of order execution 6 incorporates one floating point unit one dedicated cryptographic unit per core 7 The 64 bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor and scales up to 1 024 threads in an 8 socket system 4 Other changes include the support of PCIe version 3 0 and a new cache coherence protocol 5 Contents 1 SPARC T4 T5 and T7 M7 compared 2 SPARC T5 in systems 3 References 4 External linksSPARC T4 T5 and T7 M7 compared editThis chart shows some differences between the T5 and T4 processor chips Processor SPARC T4 4 SPARC T5 8 T7 M7 9 Max chips per system 4 8 16 Cores per chip 8 16 32 Max threads per chip 64 128 256 Frequency 2 85 3 0 GHz 3 6 GHz 4 13 GHz Shared Level 3 cache 4 MB 8 MB 64 MB MCUs per chip 2 10 4 11 4 Transfer rate per MCU 6 4 Gbit s 10 12 8 Gbit s 11 Process Technology 40 nm 28 nm 20 nm Die size 403 mm2 478 mm2 PCIe Version 2 0 3 0 3 0 The SPARC T5 also introduces a new power management feature that consists of hardware support in the processor and the software that allows system administrator to use the feature Users select the policy how the system responds to over temperature and over current events The dynamic voltage and frequency scaling aka DVFS policy can be set to maintain peak frequency or to trade off between performance and power consumption 5 SPARC T5 in systems editThe SPARC T5 processor is used in Oracle s entry and mid size SPARC T5 2 T5 4 and T5 8 servers All servers use the same processor frequency number of cores per chip and cache configuration 12 The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache Multiprocessor cache coherence is maintained using a directory based protocol 5 The design scales up to eight sockets without additional silicon glueless The snooping based protocol used in SPARC T4 systems was replaced in order to reduce memory latency and reduce coherency bandwidth consumption 5 13 References edit High Performance Security for Oracle WebLogic server Applications Using Oracle s SPARC T5 and SPARC M5 Servers White Paper PDF www oracle com Oracle Corporation May 2012 Timothy Prickett Morgan 4 September 2012 Oracle hurls Sparc T5 gladiators into big iron arena www theregister co uk The Register Timothy Prickett Morgan 26 March 2013 Oracle s new T5 Sparcs boost scalability in chip and chassis www theregister co uk The Register a b c SPARC T4 Processor Data Sheet PDF www oracle com Oracle Corporation a b c d e John Feehrer Sumti Jairath Paul Loewenstein Ram Sivaramakrishnan David Smentek Sebastian Turullols Ali Vahidsafa March April 2013 IEEE Micro vol 33 no 2 The Oracle Sparc T5 16 Core Processor Scales to Eight Sockets pp 48 57 IEEE Computer Society ISSN 0272 1732 SPARC T5 Processor Data Sheet PDF www oracle com Oracle Corporation Manish Shah Robert Golla Gregory Grohoski Paul Jordan Jama Barreh Jeff Brooks Mark Greenberg Gideon Levinsky Mark Luttrell Christopher Olson Zeid Samoail Matt Smittle Tom Ziaja March April 2012 IEEE Micro vol 32 no 2 Sparc T4 A Dynamically Threaded Server on a Chip pp 8 19 IEEE Computer Society Oracle SPARC T5 2 SPARC T5 4 SPARC T5 8 and SPARC T5 1B Server Architecture PDF Oracle Corporation Oracle SPARC T7 and SPARC M7 Server Architecture PDF www oracle com Oracle Corporation a b Oracle SPARC T4 1 SPARC T4 2 SPARC T4 4 and SPARC T4 1B Server Architecture An Oracle White Paper p 28 PDF www oracle com Oracle Corporation June 2012 a b Oracle SPARC T5 2 SPARC T5 4 SPARC T5 8 and SPARC T5 1B Server Architecture An Oracle White Paper p 29 PDF www oracle com Oracle Corporation February 2014 Jean Bozman April 5 2013 Oracle Launches T5 and M5 Servers A New Generation of Oracle s SPARC Solaris Servers IDC ISSN 0272 1732 SPARC T5 Deep Dive An interview with Oracle s Rick Hetherington www oracle com Oracle CorporationExternal links edit Retrieved from https en wikipedia org w index php title SPARC T5 amp oldid 1220804558, wikipedia, wiki, book, books, library,
