TLS acceleration (formerly known as SSL acceleration) is a method of offloading processor-intensive public-key encryption for Transport Layer Security (TLS) and its predecessor Secure Sockets Layer (SSL)[1] to a hardware accelerator.
Sun Microsystems SSL accelerator PCI card introduced in 2002
Typically this means having a separate card that plugs into a PCI slot in a computer that contains one or more coprocessors able to handle much of the SSL processing.
TLS accelerators may use off-the-shelf CPUs, but most use custom ASIC and RISC chips to do most of the difficult computational work.
The most computationally expensive part of a TLS session is the TLS handshake, where the TLS server (usually a webserver) and the TLS client (usually a web browser) agree on a number of parameters that establish the security of the connection. During the TLS handshake the server and the client establish session keys (symmetric keys, used for the duration of a given session), but the encryption and signature of the TLS handshake messages itself is done using asymmetric keys, which requires more computational power than the symmetric cryptography used for the encryption/decryption of the session data.
Typically a hardware TLS accelerator will offload processing of the TLS handshake while leaving it to the server software to process the less intense symmetric cryptography of the actual TLS data exchange, but some accelerators handle all TLS operations and terminate the TLS connection, thus leaving the server seeing only decrypted connections. Sometimes data centers employ dedicated servers for TLS acceleration in a reverse proxy configuration.
^Stewart, J. Michael; Kinsey, Denise (2020-10-15). Network Security, Firewalls, and VPNs. Jones & Bartlett Learning. ISBN978-1-284-23004-8.
^[PATCH v5] crypto: Add Allwinner Security System crypto accelerator on Linux ARM kernel mailing list
External linksedit
SSL Acceleration and Offloading: What Are the Security Implications?
January 01, 1970
acceleration, formerly, known, acceleration, method, offloading, processor, intensive, public, encryption, transport, layer, security, predecessor, secure, sockets, layer, hardware, accelerator, microsystems, accelerator, card, introduced, 2002this, article, n. TLS acceleration formerly known as SSL acceleration is a method of offloading processor intensive public key encryption for Transport Layer Security TLS and its predecessor Secure Sockets Layer SSL 1 to a hardware accelerator Sun Microsystems SSL accelerator PCI card introduced in 2002This article needs additional citations for verification Please help improve this article by adding citations to reliable sources Unsourced material may be challenged and removed Find sources TLS acceleration news newspapers books scholar JSTOR July 2023 Learn how and when to remove this message Typically this means having a separate card that plugs into a PCI slot in a computer that contains one or more coprocessors able to handle much of the SSL processing TLS accelerators may use off the shelf CPUs but most use custom ASIC and RISC chips to do most of the difficult computational work Contents 1 Principle of TLS acceleration operation 1 1 Central processor support 2 See also 3 References 4 External linksPrinciple of TLS acceleration operation editThe most computationally expensive part of a TLS session is the TLS handshake where the TLS server usually a webserver and the TLS client usually a web browser agree on a number of parameters that establish the security of the connection During the TLS handshake the server and the client establish session keys symmetric keys used for the duration of a given session but the encryption and signature of the TLS handshake messages itself is done using asymmetric keys which requires more computational power than the symmetric cryptography used for the encryption decryption of the session data Typically a hardware TLS accelerator will offload processing of the TLS handshake while leaving it to the server software to process the less intense symmetric cryptography of the actual TLS data exchange but some accelerators handle all TLS operations and terminate the TLS connection thus leaving the server seeing only decrypted connections Sometimes data centers employ dedicated servers for TLS acceleration in a reverse proxy configuration Central processor support edit Modern x86 CPUs support Advanced Encryption Standard AES encoding and decoding in hardware using the AES instruction set proposed by Intel in March 2008 Allwinner Technology provides a hardware cryptographic accelerator in its A10 A20 A30 and A80 ARM system on chip series and all ARM CPUs have acceleration in the later ARMv8 architecture The accelerator provides the RSA public key algorithm several widely used symmetric key algorithms cryptographic hash functions and a cryptographically secure pseudo random number generator 2 See also editStunnel Application delivery controller Hardware security moduleReferences edit Stewart J Michael Kinsey Denise 2020 10 15 Network Security Firewalls and VPNs Jones amp Bartlett Learning ISBN 978 1 284 23004 8 PATCH v5 crypto Add Allwinner Security System crypto accelerator on Linux ARM kernel mailing listExternal links editSSL Acceleration and Offloading What Are the Security Implications Retrieved from https en wikipedia org w index php title TLS acceleration amp oldid 1182622875, wikipedia, wiki, book, books, library,
