In a uniprocessor system (where there exists only one core), there is only one processing element doing all the work and therefore only one processing element that can read or write from/to a given memory location. As a result, when a value is changed, all subsequent read operations of the corresponding memory location will see the updated value, even if it is cached.
Conversely, in multiprocessor (or multicore) systems, there are two or more processing elements working at the same time, and so it is possible that they simultaneously access the same memory location. Provided none of them changes the data in this location, they can share it indefinitely and cache it as they please. But as soon as one updates the location, the others might work on an out-of-date copy that, e.g., resides in their local cache. Consequently, some scheme is required to notify all the processing elements of changes to shared values; such a scheme is known as a memory coherence protocol, and if such a protocol is employed the system is said to have a coherent memory.
The exact nature and meaning of the memory coherency is determined by the consistency model that the coherence protocol implements. In order to write correct concurrent programs, programmers must be aware of the exact consistency model that is employed by their systems.
When implemented in hardware, the coherency protocol can, for example, be directory-based or snooping-based (also called sniffing). Specific protocols include the MSI protocol and its derivatives MESI, MOSI and MOESI.
^Censier, L.M.; Feautrier, P. (December 1978). "A New Solution to Coherence Problems in Multicache Systems". IEEE Transactions on Computers. C-27 (12): 1112–18. doi:10.1109/TC.1978.1675013. S2CID 5898229.
^Smith, Alan Jay (September 1982). "Cache Memories". ACM Computing Surveys. 14 (3): 473–530. doi:10.1145/356887.356892. S2CID 6023466.
^Li, Kai; Hudak, Paul (November 1989). "Memory coherence in shared virtual memory systems". Transactions on Computer Systems. 7 (4): 321–59. doi:10.1145/75104.75105. S2CID 1678750.
^Stenstrom, Per (June 1990). "A survey of cache coherence schemes for multiprocessors". IEEE Computer. 23 (6): 12–24. doi:10.1109/2.55497.
April 11, 2024
memory, coherence, issue, that, affects, design, computer, systems, which, more, processors, cores, share, common, area, memory, uniprocessor, system, where, there, exists, only, core, there, only, processing, element, doing, work, therefore, only, processing,. Memory coherence is an issue that affects the design of computer systems in which two or more processors or cores share a common area of memory 1 2 3 4 In a uniprocessor system where there exists only one core there is only one processing element doing all the work and therefore only one processing element that can read or write from to a given memory location As a result when a value is changed all subsequent read operations of the corresponding memory location will see the updated value even if it is cached Conversely in multiprocessor or multicore systems there are two or more processing elements working at the same time and so it is possible that they simultaneously access the same memory location Provided none of them changes the data in this location they can share it indefinitely and cache it as they please But as soon as one updates the location the others might work on an out of date copy that e g resides in their local cache Consequently some scheme is required to notify all the processing elements of changes to shared values such a scheme is known as a memory coherence protocol and if such a protocol is employed the system is said to have a coherent memory The exact nature and meaning of the memory coherency is determined by the consistency model that the coherence protocol implements In order to write correct concurrent programs programmers must be aware of the exact consistency model that is employed by their systems When implemented in hardware the coherency protocol can for example be directory based or snooping based also called sniffing Specific protocols include the MSI protocol and its derivatives MESI MOSI and MOESI See also editCache coherence Distributed shared memory Race conditionReferences edit Censier L M Feautrier P December 1978 A New Solution to Coherence Problems in Multicache Systems IEEE Transactions on Computers C 27 12 1112 18 doi 10 1109 TC 1978 1675013 S2CID 5898229 Smith Alan Jay September 1982 Cache Memories ACM Computing Surveys 14 3 473 530 doi 10 1145 356887 356892 S2CID 6023466 Li Kai Hudak Paul November 1989 Memory coherence in shared virtual memory systems Transactions on Computer Systems 7 4 321 59 doi 10 1145 75104 75105 S2CID 1678750 Stenstrom Per June 1990 A survey of cache coherence schemes for multiprocessors IEEE Computer 23 6 12 24 doi 10 1109 2 55497 Retrieved from https en wikipedia org w index php title Memory coherence amp oldid 1174158964, wikipedia, wiki, book, books, library,
