Delay insensitive circuit

A delay-insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip. Instead of using clock signals or other global control signals, the sequencing of computation in delay-insensitive circuit is determined by the data flow.

Data flows from one circuit element to another using "handshakes", or sequences of voltage transitions to indicate readiness to receive data, or readiness to offer data. Typically, inputs of a circuit module will indicate their readiness to receive, which will be "acknowledged" by the connected output by sending data (encoded in such a way that the receiver can detect the validity directly^[1]), and once that data has been safely received, the receiver will explicitly acknowledge it, allowing the sender to remove the data, thus completing the handshake, and allowing another datum to be transmitted.

In a delay-insensitive circuit, there is therefore no need to provide a clock signal to determine a starting time for a computation. Instead, the arrival of data to the input of a sub-circuit triggers the computation to start. Consequently, the next computation can be initiated immediately when the result of the first computation is completed.

The main advantage of such circuits is their ability to optimize processing of activities that can take arbitrary periods of time depending on the data or requested function. An example of a process with a variable time for completion would be mathematical division or recovery of data where such data might be in a cache.

The Delay-Insensitive (DI) class is the most robust of all asynchronous circuit delay models. It makes no assumptions on the delay of wires or gates. In this model all transitions on gates or wires must be acknowledged before transitioning again. This condition stops unseen transitions from occurring. In DI circuits any transition on an input to a gate must be seen on the output of the gate before a subsequent transition on that input is allowed to happen. This forces some input states or sequences to become illegal. For example OR gates must never go into the state where both inputs are one, as the entry and exit from this state will not be seen on the output of the gate. Although this model is very robust, no practical circuits are possible due to the lack of expressible conditionals in DI circuits.^[2] Instead the Quasi-Delay-Insensitive model is the smallest compromise model yet capable of generating useful computing circuits. For this reason circuits are often incorrectly referred to as Delay-Insensitive when they are Quasi Delay-Insensitive.

See also

• self-clocking signal
• delay-tolerant networking

References

1. Verhoeff, Tom (January 1987). "Delay-Insensitive Codes--An Overview".
2. Martin, Alain. "The Limitations to Delay-Insensitivity in Asynchronous Circuits" (PDF).

External links

• "Delay-Insensitive Codes -- An Overview" by Tom Verhoeff
• "TITAC: Design of A Quasi-Delay-Insensitive Microprocessor" by Takashi Nanya et al. 1994
• "A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems" by Pedro A. Molina and Peter Y. K. Cheung 1997
• "Quasi-Delay-Insensitive Circuits are Turing-Complete" by Manohar, Rajit and Martin, Alain J. (1995)
• "EDIS, the Encyclopedia of Delay-Insensitive Systems" edited by Tom Verhoeff